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Modeling >> Semiconductor Devices >> saturation
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Message started by safwatonline on Dec 8^th, 2005, 4:37am

Title: saturation
Post by safwatonline on Dec 8^th, 2005, 4:37am

hello,
this is my first post here , i am new to analog design in general , i am using orcad 9 , in my bias point simulation i found that the parameter Lin0/sat1 equal =-1
does this mean that this mos is in saturation also why is the -ve sign ,
another question is that if i have vds>vgs-vth , but vds<vdsat
and lin0/sat1 equal -1 is this in sat.

Title: Re: saturation
Post by Geoffrey_Coram on Dec 15^th, 2005, 8:39am

I've never used orcad9, so I'm not familiar with lin0/sat1; can you look it up in the documentation?

As to vdsat: I think vdsat from channel pinch-off is related to vgs-vth, and you can also have saturation due to velocity saturation. However, I'd expect velocity saturation to lower vdsat, so I'm not sure how you get vds>vgs-vth and vds<vdsat.

Title: Re: saturation
Post by Marc Murphy on Feb 8^th, 2006, 3:41pm

For short-channel devices, velocity saturation makes Vds,sat < Vgs - Vth. Most people refer to Vgs - Vth as Vov (overdrive).

If you are biased such that Vov is very small, I think it's possible that Vds > Vov but it is still not larger than Vds,sat.

The key point here is that Vds,sat != Vgs - Vth.