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Message started by dot13 on Dec 8th, 2005, 5:54am

Title: balun model
Post by dot13 on Dec 8th, 2005, 5:54am

Hi, everyone
I need a balun with such performance: when the single-end port is floating or load 50 ohms, add a signal to one of the unbalanced-end, the other port will get a 180 degree inverse signal to the input, and the same p-p voltage.
I found that the balun model in the rfLib can't  reach my demand. When I add a signal to one of the unbalanced-end with the other two ports load 50 ohms, the single-end port have a signal, but the other unbalanced-end get nothing.  
So I modified the veriloga file as following, but I don't konw if it is correct. Could someone tell me? Thanks.

module balun(single, bal_p, bal_n);
 inout single, bal_p, bal_n;
 electrical single, bal_p, bal_n;
  parameter real rin = 50 from (0:inf);
  parameter real rout = 50 from (0:inf);
  parameter real loss = 0 from [0:inf);

  real      a1, a2, a3;
  real      s21, s31, s12, s13, s23, s32;

  electrical single_int, bal_p_int, bal_n_int;

  analog begin

     @(initial_step("static") or initial_step("pss") or
     initial_step("pdisto")) begin
      // unfold the S parameters from dB to real values
      s21 = pow(10,-loss/20);
      s21 = s21/sqrt(2.0);    // energy converation law!
      s31 = -s21;
      s12 = s21;
      s13 = s31;
      s23 = -1;      
      s32 = -1;      
     end

     // calculate the normalized incident waves: a1, a2
     a1 = V(single)/sqrt(rin) + I(single, single_int)*sqrt(rin);
     a2 = V(bal_p)/sqrt(rout) + I(bal_p, bal_p_int)*sqrt(rout);
     a3 = V(bal_n)/sqrt(rout) + I(bal_n, bal_n_int)*sqrt(rout);
     
     // input
     // be careful about the sign of the controlled source
     I(single_int) <+ V(single)/rin;
     I(single_int) <+ -a2*s12/sqrt(rin);
     I(single_int) <+ -a3*s13/sqrt(rin);
     
     // output positive node
     I(bal_p_int) <+ V(bal_p)/rout;
     I(bal_p_int) <+ -a1*s21/sqrt(rout);
     I(bal_p_int) <+ -a3*s23/sqrt(rout);
     
     // output negative node
     I(bal_n_int) <+ V(bal_n)/rout;
     I(bal_n_int) <+ -a1*s31/sqrt(rout);
     I(bal_n_int) <+ -a2*s32/sqrt(rout);

  end
endmodule // balun

Title: Re: balun model
Post by Jess Chen on Dec 8th, 2005, 1:06pm

Could you post a schematic or netlist showing how you are trying to use the balun model? I am having trouble visualizing your test bench.

-Jess

Title: Re: balun model
Post by dot13 on Dec 8th, 2005, 8:57pm

Thanks for reply
This is my test-bench netlist:

Balun1 (single bal_p bal_n) balun rin=50 rout=50 loss=0
R0 (single 0) resistor r=50
R1 (bal_n 0) resistor r=50
PORT0 (bal_p 0) port r=50 num=1 type=sine dbm=-30 sinephase=0 freq=1G \\
       mag=1 phase=0 xfmag=1 pacmag=1 fundname=\"fre\"
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \\
   tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \\
   digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \\
   sensfile=\"../psf/sens.output\"
tran tran stop=2n errpreset=moderate write=\"spectre.ic\" \\
   writefinal=\"spectre.fc\" annotate=status maxiters=5

Sorry that I don\'t konw how to insert a picture.

Title: Re: balun model
Post by Jess Chen on Dec 9th, 2005, 9:50am

I see your point. I think there's an easier solution. The rfLib balun is implemented with s-parameters, which makes it hard to follow. There's a much easier approach as long as you do not drive or load with idea sources. I use one vcvs and one cccs. It's an old power electronics trick for modeling an ideal dc/dc transformer. I think this model does what you want; this model exhibits the correct signal on the other "unbalanced" pin. However, I believe that signal should be in phase with the driving signal if I understood your initial statement. I've included a netlist. The netlist includes a test of the rfLib balun too.

-Jess

// Generated for: spectre
// Generated on: Dec  9 09:46:44 2005
// Design library name: jess
// Design cell name: baluntest
// Design view name: schematic
simulator lang=spectre
global 0
include "/cad/cadence/tools.sun4v/dfII/samples/artist/ahdlLib/quantity.spectre"

// Library name: jess
// Cell name: baluntest
// View name: schematic
F0 (net014 net015) cccs gain=sqrt(50.0/150.0) probe=V0
E0 (net028 net019 net015 0) vcvs gain=sqrt(50.0/150.0)
V0 (net019 0) vsource type=dc
PORT1 (net015 0) port r=50 type=sine freq=1M ampl=1
PORT0 (net9 0) port r=50 type=sine freq=1M ampl=1
R3 (net014 0) resistor r=50
R2 (net028 0) resistor r=50
R1 (net8 0) resistor r=50
R0 (net6 0) resistor r=50
I0 (net6 net9 net8) balun rin=50 rout=50 loss=0
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
   tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
   digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \
   sensfile="../psf/sens.output"
tran tran stop=2u write="spectre.ic" writefinal="spectre.fc" \
   annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
saveOptions options save=allpub
ahdl_include "/auto/cadtools/ic5033f/tools.sun4v/dfII/samples/artist/rfLib/balun/veriloga/veriloga.va"

Title: Re: balun model
Post by dot13 on Dec 15th, 2005, 5:44am

Thanks. I think I got it.
But there is another question. You put several resistors in the model, so the input (and output) impedance is 50 ohms. But I am quite doubt that does the actual balun have this performance? That means, for a certain frequency (or a wide-band use), the balun can show a impedance of 50 ohms at all the three ports?
If so, what does the "50 ohms" comes? Doesn't a balun made of  inductor/transfermor?
While if not, why do we simulate our schematic use the unrealistic balun model?

Title: Re: balun model
Post by Jess Chen on Dec 15th, 2005, 7:44am

I did not need so many resistors. I just slapped together an example. My simulation environment complains if I leave terminals unconnected. I only wanted to send you a complete test circuit, not just the model. The model only consists of the controlled sources. Everything else belongs to the test bench. The simple model I gave represents an ideal transformer, one that works even at DC. The turns ratio, or gain of the controlled sources, equals the square root of the impedance ratio you want. There is only one caution: be careful connecting ideal sources to the model. Looking into one side, you see a voltage source. You will not be able to drive or load that terminal with another ideal voltage source. Looking into the other side, you see a current source. You will not be able to load or drive that terminal with an ideal current source. If your loads and sources have finite impedances, you should have no trouble. Aside from these mathematical limitations, the only other relevant unrealistic aspects of the model are that it has absolutely no frequency dependence and will never saturate. However, it is not hard to add those effects if you can quantify them.

The model can easily be expanded to model multiple windings on one transformer core.

-Jess

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