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https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Please Have a Look.. Layout Questions.. https://designers-guide.org/forum/YaBB.pl?num=1134152707 Message started by Sezi on Dec 9th, 2005, 10:25am |
Title: Please Have a Look.. Layout Questions.. Post by Sezi on Dec 9th, 2005, 10:25am Hello, I have some practical questions on the layout of mixed-signal circuits. I'll appreciate even if you only answer one of the following questions.. 1.. When drawing the layout of a MOS, is it a good idea to put M1-M2 (matel1-metal2) and M2-M3.. contacts directly on the drain/source area of the transistor, just beside the gate? Or is it better to extend the M1 outside of the MOS and put all the contacts on the extension? 2.. What's the most effective and best way to connect the fingered transistors' gates and other terminals to each other? I have read somewhere that connecting the gate fingers directly with poly is not a good idea? 3.. Is it better to start connecting the terminals other than vdd and gnd first with lower layer metals, and then in the end merging the vdd and gnd nets of all blocks with higher level metals? Is it better to use higher level metal for vdd/gnd? 4.. When making large layouts consisting of sub-blocks, how to achieve compact layouts with these sub-blocks with different sizes and shapes? Do we fill the spaces with bulk contacts? or how do we avoid these spaces? 5.. When making the layout of a PLL, is it better to group the digital components(PFD, divider..) and surround them with guard rings and place them apart from the analog blocks (VCO, charge pump, bias generator etc..)? What is the usual strategy? Thanks in advance! Sezi |
Title: Re: Please Have a Look.. Layout Questions.. Post by Paul on Dec 10th, 2005, 12:11pm Hi Sezi, very interesting questions. As layout is more of a cookbook type of approach, with each cook having his own receipes, you shouldn't expect everybody to provide similar answers. My very personal point of view to your questions: 1. In modern technologies, via stacks should be quite well behaved (in some older ones they may not be allowed). As long as all transistors see the same stack, matching should not be affected. 2. Poly has higher series resistance than metal. Poly routing potentially lowers your transistor cut-off frequency, which is not shown in simulation, unless you do RC-extraction based post-layout simulation. In low-frequency designs, some poly routing may still be OK. 3. This depends on your system-level supply routing strategy. My general rule is to route for minimum series resistance in the supply connections. 4. Try to thinl about block assembly before drawing sub-block layouts. In this way, you know what shape you want each sub-block to have, including its terminal placements. Spending some time with this will save a lot of time in the assembly process. 5. I would say, try to separate noisy blocks from sensitive blocks. Depending on your charge pump design, it may be much noisier than the divider or the PFD... I hope you will get other opinions to compare with. Paul |
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