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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> instantiation of modules https://designers-guide.org/forum/YaBB.pl?num=1134597588 Message started by sylak on Dec 14th, 2005, 1:59pm |
Title: instantiation of modules Post by sylak on Dec 14th, 2005, 1:59pm hi all, 1. I get the 'segmentation violation' error when I instantiate this nand module nand_gate #(.vlogic_high(1.2),.vlogic_low(0),.vtrans(0.54),.tdel(10p),.trise(20p),.tfall(20p)) Nand(a1,b1, out); vlogic_high,vlogic_low ..etc are parameters declared in the module. and I want to connect the 'in1' 'in2' and 'out' of the nand module to 'a1' 'b1' and 'out' I am not sure as what the error signifies! 2. when instantiation , do the modules have to declared in "`include " I looked at various examples in this website, they were not declared. Does this assume the modules to be in the same directory. I have tried the simualtion by including the module path using the `include ' /path/nand.va' ... doesnt seem to make a difference as far as the error message is concerned but Would like to know if this is necessary. Thanks in advance! S |
Title: Re: instantiation of modules Post by Geoffrey_Coram on Dec 15th, 2005, 8:59am I include .va models in Spectre netlists with ahdl_include "/path/nand.va" It appears you have a Verilog netlist, so the `include should be correct there. Does spectre read Verilog netlists? How do you specify the analyses? |
Title: Re: instantiation of modules Post by sylak on Dec 16th, 2005, 1:38pm Geoffry, Thank you for replying! I dont use spectre to run simulations. I use hsim which supports veriloga modules. so I write the testbench in spice and use '.hsimveriloga' statement to define the path to the veriloga module. I have the nand gate written in veriloga and it seems to work fine when I run the simulations. I seem to have trouble only when I write a veriloga code to instantiate a module. I have no idea as what the error means. dont know which directions to look to correct the error- the simulator, the code or the testbench. ?. Just posted it here to see if any one had this kind of problem before. S |
Title: Re: instantiation of modules Post by Geoffrey_Coram on Dec 21st, 2005, 7:58am A "segmentation violation" is usually an indication of a bug in the executable: part of the program is trying to access memory that is not associated with the program, probably a pointer that wasn't updated. So, I might suggest sending a test case off to the HSIM support folks. |
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