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Design Languages >> Verilog-AMS >> Verilog-a vs. Verilog-ams
https://designers-guide.org/forum/YaBB.pl?num=1134750854

Message started by mrbrown on Dec 16^th, 2005, 8:34am

Title: Verilog-a vs. Verilog-ams
Post by mrbrown on Dec 16^th, 2005, 8:34am

What is the difference between Verilog-a and Verilog-ams?

Thanks.

Title: Re: Verilog-a vs. Verilog-ams
Post by Geoffrey_Coram on Dec 21^st, 2005, 7:59am

Verilog-A is a subset of Verilog-AMS. Verilog-AMS has a language reference manual (LRM) available from http://www.eda.org/verilog-ams, and one of the appendices specifies what subsets of the LRM are part of Verilog-A.

The idea is that Verilog-A should consist only of things that can be simulated in an analog (spice-like) simulator. AMS includes digital things and generally requires a second (digital) simulator running with the analog simulator.

Title: Re: Verilog-a vs. Verilog-ams
Post by Kenneth Brun Nielsen on Dec 21^st, 2005, 8:01am

OK. That makes sense. Thanks!

/Kenneth