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Design >> Mixed-Signal Design >> differential clocks for pipelined ADCs
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Message started by vivkr on Dec 20^th, 2005, 8:14am

Title: differential clocks for pipelined ADCs
Post by vivkr on Dec 20^th, 2005, 8:14am

Hi,

Does differential clocking offer significant advantages in pipelined ADCs?

If so, then what are these advantages and how does one apply differential clocking for maximum benefit, and with minimum overhead?

Thanks
Vivek

Title: Re: differential clocks for pipelined ADCs
Post by ywguo on Dec 27^th, 2005, 7:20am

Hi, vivkr,

As well known, the clock jitter deteriorate the performance of the ADC, especially that of high speed ADC. And differetial clock is more robust than single-ended clock.

Differential signals like LVDS is a good choice to minimize clock jitter on a PCB board, or in an SOC.

Best regards,
Yawei

Title: Re: differential clocks for pipelined ADCs
Post by vivkr on Dec 28^th, 2005, 12:42am

Hi Yawei,

Many thanks for the response.

I can understand that routing the clocks differentially makes them more
robust to on-board interference. But how does one use them with an ADC?

I mean you will be generating the non-overlapping phases inside the ADC for timing. How does one make use of two complementary clocks in this? Does it make no difference on-chip, where I just treat one signal as the inverted version of the other, or can something special be done?

Also, most signal sources are single-ended, so one needs to add some circuitry to convert the signals to fully-differential level, and to buffer these (maybe not needed for clocks). Does this not add some jitter?

Any suggestions or links will be most welcome.

Regards
Vivek