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Design Languages >> Verilog-AMS >> trying to check my schematic
https://designers-guide.org/forum/YaBB.pl?num=1135171205

Message started by saad74 on Dec 21^st, 2005, 5:20am

Title: trying to check my schematic
Post by saad74 on Dec 21^st, 2005, 5:20am

Hi everybody,

After facing several schematic related errors I have decided to learn verilog atleast to perform basic simulation.
I want to know whether it is possible to check this schematic error or not.

- I have two components in my design (i1 & i2).
- Each pin has its associated net name with a prefix 'net_'
- Component i2 has an error (interchange of net scl <-> sda) --> please the model below.

How can I check this error?
I am using Cadence Concept HDL tool which has created following model for my components.

Please use the example below for suggestions.
I'll appreciate any help.

Thanks,
Saad.

--------------------------------
`timescale 1ns/1ns

module dummy_root_design ();

wire gnd;
wire net_a0;
wire net_a1;
wire net_a2;
wire net_scl;
wire net_sda;
wire net_wp;
wire vcc;

// begin instances

eeprom_master page1_i1 (.a0(net_a0),
.a1(net_a1),
.a2(net_a2),
.gnd(gnd),
.scl(net_sda),
.sda(net_scl),
.vcc(vcc),
.wp(net_wp));

eeprom_master page1_i2 (.a0(net_a0),
.a1(net_a1),
.a2(net_a2),
.gnd(gnd),
.scl(net_scl),
.sda(net_sda),
.vcc(vcc),
.wp(net_wp));

endmodule // dummy_root_design(sch_1)

Title: Re: trying to check my schematic
Post by Marq on Jan 10^th, 2006, 12:21am

In general the language will not help you check for these kinds of errors, because they require interpretation of the name. Even more so, in synthesized Verilog the names will be completely meaningless. You can better try write a Perl or Python script to verify the netlist against some of the coding rules you apparently use.

The right way to check for these kinds of errors is by means of functional verification: make a test bench in Verilog that generates a couple of relevant test vectors (bit patterns) on all inputs, determine what the outputs should be for the given input patterns, and perform the simulation to verifiy that the predetermined answers fit your simulation results.

Regards,
Marq