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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Phase domain model of DLL https://designers-guide.org/forum/YaBB.pl?num=1135346601 Message started by ggr on Dec 23rd, 2005, 6:03am |
Title: Phase domain model of DLL Post by ggr on Dec 23rd, 2005, 6:03am HI, how to model VCDL in phase domain? I extracted the phase noise from the blocks of a DLL. what changes to be made to the models given in the PLL Noise paper so that I can include those extracted parameters? thanks rs |
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