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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> OTA verilog-AMS model https://designers-guide.org/forum/YaBB.pl?num=1135420142 Message started by Visjnoe on Dec 24th, 2005, 2:29am |
Title: OTA verilog-AMS model Post by Visjnoe on Dec 24th, 2005, 2:29am Hi, I'm a bit stuck on generating a realistic OTA model, especially with regard to slewrate. My main idea was to implement a simple small-signal model for the OTA, something like this: I(out) <+ gm*V(inp,inn); I(out) <+ V(out)/rout; This approximation is valid in the region abs(V(inp,inn)) < SQRT(2)*(Vgs-Vt) with Vgs-Vt the (equilibrium) overdrive voltage of the differential input pair. This is in fact the classic 'gm*Rout' model of a simple OTA. Now, I could include slewrate limiting by using the slew() function on the OTA output. However, I would like to be able to use the OTA in different surroundings, meaning that I would like to provide some sort of maximum current for the OTA and then let the slewrate arise from the capacitive load the OTA sees at its output. In contrast, the slew() function imposes a minimum/maximum slewrate, independent of the capacitive load/OTA surroundings. I find this to be a disadvantage for system-level design. Now, my problem is to unify the small-signal (gm*Rout) model and the slew-rate behavior of the OTA, which is clearly large signal. At the moment, I only see 1 solution: if the input voltage is smaller than SQRT(2)*(Vgs-Vt) I implement the behavior is shown in the code above and otherwise I would implement it as follows: I(out) <+ Imax*dir; (dir being -1 or 1) So, using different branch contributions for small-signal and for large-signal behavior. Does anyone have some experience with this? All comments are welcome. Although being regarded as a basic building block, how come I find a OTA harder to model than most other blocks?:) Kind Regards Peter |
Title: Re: OTA verilog-AMS model Post by sheldon on Dec 24th, 2005, 4:28am Peter, Try limiting the gm * Vin function. You can use the arctangent function or something like I( out) <+ 1/ ( 1/ gm *V(inp, inn) ) + ( 1 / Imax) ; This functions limits the output current gm * V(inp,inn) >> Imax --> Imax gm * V(inp,inn) << Imax --> gm * V(inp, inn) gm * V(inp,inn) = Imax --> gm * V(inp,inn)/2 The sign can be handle inside of arctangent function. You will still need to figure out the sign separately using this approach. It can be computationally expensive to exactly mimic the MOS differential pairs limiting characteristics. Best Regards, Sheldon |
Title: Re: OTA verilog-AMS model Post by Visjnoe on Dec 26th, 2005, 4:17am Sheldon, thanks a lot for your answer. I was aware of the tanh() approach, but your alternative was new to me. Kind Regards Peter |
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