The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> high linearity sampling without bootstrapping
https://designers-guide.org/forum/YaBB.pl?num=1135783944

Message started by vivkr on Dec 28^th, 2005, 7:32am

Title: high linearity sampling without bootstrapping
Post by vivkr on Dec 28^th, 2005, 7:32am

Hi,

I am wondering if there are any good options to get very high sampling linearity
if bootstrapping is not possible. I am trying to sample a sinewave in the range of 1MHz with about 14-bit linearity.

Normally, I favor bootstrapping but I cannot use it in my application. Is there any other possible option?

Thanks
Vivek

Title: Re: high linearity sampling without bootstrapping
Post by Paul on Dec 29^th, 2005, 1:02pm

Hi Vivek,

if linearity is your only constraint (which is probably not the case), restricting your input signal to a smaller range should improve the results, of course at reduced SNR. Prober selection of the common mode voltage (respectively the DC level for single-ended signals) also helps.

Not sure whether this is the kind of answer you were looking for...

Paul

Title: Re: high linearity sampling without bootstrapping
Post by venky on Dec 29^th, 2005, 7:38pm

Hi,
If the signal is low frequency(i assume the process you are using is fast)
then you can use a cascade of two tracking amplifier with sampling switch
between the two amps. This way the switch doesnt see any signal and hence very highly linear.

Title: Re: high linearity sampling without bootstrapping
Post by sheldon on Dec 30^th, 2005, 3:02am

Vivek,

This is a tough question, as you can see there are
different thoughts on this topic. Bootstrapping comes
from the "let's design a more complex circuit to
compensate for the non-idealities" school of thought.
Another approach is to make things as "simple as
possible to eliminate sources on non-ideality", please
see the following paper:

"A 3-V 340-mW 14-b 75-Msample/s CMOS ADC With
85-dB SFDR at Nyquist Input," Wenhua (Will) Yang,
Member, IEEE, Dan Kelly, Member, IEEE, Iuri Mehr,
Member, IEEE, Mark T. Sayuk, Member, IEEE, and Larry
Singer, Member, IEEE

The sample and hold is reduced to a switch and a
capacitor to minimize non-idealities. Given your
targets the simple is best approach may be an
appropriate one. The main constraint of this approach
is the common-mode rejection of the op-amp and
it should be possible to design an op-amp with
good common-mode rejection at 1MHz.

Best Regards,

Sheldon