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Design >> Analog Design >> How to analyze each leakage current using HSPICE
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Message started by ipierre on Dec 28^th, 2005, 11:51pm

Title: How to analyze each leakage current using HSPICE
Post by ipierre on Dec 28^th, 2005, 11:51pm

How to analyze each leakage current(in MOSFET) using HSPICE?

For example,

.print i1(nmos) <- I(drain)
.print lx5(nmos) <- I(souce-bulk)

But, I don't know how to simulate each leakage current as below,

sub-threshold leakage,
Source/Drain Junction Band-to-Band Tunneling leakage,
gate-leakage,
gate-induced drain leakage.

please let me know...

Thanks in advance.

iPierre.

Title: Re: How to analyze each leakage current using HSPI
Post by Geoffrey_Coram on Jan 3^rd, 2006, 5:43am

In general, commercial simulators don't allow you to break out the different components of the current. That is, the drain current includes gate-induced drain leakage and the (negative of the) body-drain diode current including the band-to-band tunneling. If you use Berkeley Spice, you can modify the source code to print out the values of the different components that are amalgamated.

For some items, the HSpice element templates do allow you to print the values. For example, I see that "LX70" is "igidlo", the gate-induced drain leakage for level=54 (BSIM4). I think the format for these is:

Code:

.print nmos:LX70

or

Code:

.print nmos:igidlo

But you have to look carefully at the mosfet level to see what is supported. (Eg, LX47 is IGIDL for levels 57,58,59, but is described as "GIDL current Meyer and Charge Conservation" which is probably not what you wanted.)