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Design Languages >> Verilog-AMS >> CCCS in verilog AMS not working
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Message started by Saroj Rout on Dec 29^th, 2005, 2:31pm

Title: CCCS in verilog AMS not working
Post by Saroj Rout on Dec 29^th, 2005, 2:31pm

I am modeling a current-controlled-current-source in the following way.

`include "disciplines.vams"
`include "constants.vams"

module cccs_int (inp,inn,outp,outn)

input inp;
input inn;
output outp;
output outn;

electrical inp;
electrical inn;
electrical outp;
electrical outn;

parameter gain=1.0;

analog begin
I(outp,outn) <+ gain*I(inp,inn);
end

endmodule

When I terminate the output with a resistor it seems to be working fine. But when I terminat it with a capacitor, I was expecting a integrated output but the output seems to be some very High constant voltage instead.

Does anybody know why the cap is not integrating the output of the controlled current source ?

Thanks in advance.

Title: Re: CCCS in verilog AMS not working
Post by Ken Kundert on Dec 29^th, 2005, 5:24pm

You probably need to give an initial condition on the capacitor. The large voltage on the capacitor probably stems from the initial DC analysis that precedes the transient.

-Ken