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Design Languages >> Verilog-AMS >> syntax error `include
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Message started by billtsang on Jan 7^th, 2006, 9:34am

Title: syntax error `include
Post by billtsang on Jan 7^th, 2006, 9:34am

Hi,
I got syntax error when i " `include "constants.h" ". Can anyone point out the reason.

Error found by spectre during AHDL read-in.
"th.def", line 10: "`<<--? include "constants.h""
"th.def", line 10: Error: syntax error
"th.def", line 14: "electrical <<--? Pin, Nin, Pout, Nout ;"
"th.def", line 14: Error: invalid module terminal type (*undef*) for
Pout.
"th.def", line 14: Error: invalid module terminal type (*undef*) for
Nout.
"th.def", line 14: Error: invalid module terminal type (*undef*) for Pin.
"th.def", line 14: Error: invalid module terminal type (*undef*) for Nin.
"th.def", line 14: Error: syntax error
Maximum allowable errors exceeded. Exiting SpectreHDL compilation....

// Periodic Track & Hold
//
// Works with SpectreRF (has no hidden state)
// Almost ideal ...
// Has buffered input and output (infinite input Z, zero out Z)
// Exhibits no offset or distortion errors
// Only nonideality is finite aperture time and very small amount of droop

`include "constants.h"
`include "disciplines.h"

module th (Pout, Nout, Pin, Nin) (period, delay, aperture, tc)
electrical Pin, Nin, Pout, Nout ;
input Pin, Nin;
output Pout, Nout;
parameter real period=16n from (0:inf);
parameter real delay=0 from (0:inf);
parameter real aperture=period/2 from (0:period/2);
parameter real tc=aperture/10 from (0:aperture);

integer n;
real tstart, tstop;
electrical hold;

analog begin

// Determine the point where the aperture begins;
n = ($abstime - delay + aperture) / period + 0.5;
tstart = n*period + delay - aperture;
@(timer(tstart));

// Determine the time where the aperture ends;
n = ($abstime - delay) / period + 0.0;
tstop = n*period + delay;
@(timer(tstop));

// Implement switch with effective series resistence of 1 Ohm
if (($abstime > tstop - aperture) && ($abstime <= tstop))
I(hold) <+ V(hold) - V(Pin, Nin);
else
I(hold) <+ 1.0e-12 * V(hold);

// Implement capacitor with an effective capacitance of tc
I(hold) <+ tc * ddt(V(hold));

// Buffer output
V(Pout, Nout) <+ V(hold);

// Control time step tightly during aperture and loosely otherwise
if (($abstime >= tstop - aperture) && ($abstime < tstop)) begin
$bound_step(tc);
end else begin
$bound_step(period/5);
end

end
endmodule

Title: Re: syntax error `include
Post by Andrew Beckett on Jan 9^th, 2006, 11:38am

A few points:

1. Don't give the filename the suffix ".def". This tells the ahdl_include in spectre that the file is spectreHDL, not
Verilog-A. Your code is (mostly) VerilogA - the bits which aren't is probably a mistake...
2. You list the parameter names on the module line. That's spectreHDL syntax, and shouldn't be there for Verilog-A.
So the module line should just be:

Code:

module th (Pout, Nout, Pin, Nin);

3. Put the electrical definition after the port directions. It will work in spectre (with a warning these days), but in other tools they may be more strict and require the port direction before the discipline. For example:

Code:

module th (Pout, Nout, Pin, Nin);
input Pin, Nin;
output Pout, Nout;
electrical Pin, Nin, Pout, Nout ;

4. delay is a reserved word. I had to change the parameter to something else (I used "del").

Title: Re: syntax error `include
Post by Andrew Beckett on Jan 9^th, 2006, 11:39am

I meant to say that after all that, it compiles in both spectre and AMS Designer. I didn't check that the code works 8-)

Andrew.

Title: Re: syntax error `include
Post by jbdavid on Jan 10^th, 2006, 4:41am

In verilog - the parameters (if included in the module declaration header ) go BEFORE the pin declarations..
I've never used this feaure of Verilog2001 ..
jbd