The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Circuit Simulators >> Co-simulation of Analog & Digital cells in Cadence
https://designers-guide.org/forum/YaBB.pl?num=1136883414

Message started by moisiad on Jan 10^th, 2006, 1:06am

Title: Co-simulation of Analog & Digital cells in Cadence
Post by moisiad on Jan 10^th, 2006, 1:06am

Hi all

I am doing analog design in cadence enviroment using Spectre. Can you please inform me how can i
co-simulate analog cells (in schematic view) with digital cells (in verilog).

Thanks

Title: Re: Co-simulation of Analog & Digital cells in Cad
Post by Andrew Beckett on Jan 10^th, 2006, 3:11am

Best thing is to tell you about the available tools, then you can read the documentation. It's not exactly a 2 line answer to tell you exactly how to do this...

The best solution is to use AMS Designer. This can be run from the Analog Design Environment (choose the simulator "ams"), or as a plugin in the hierarchy editor, or can be run from the command line. It's built using the digital "NC" tools, together with either the spectre or ultrasim engine as the analog solver, to form a single executable simulator.
Look in <instdir>/doc/amsenvug/amsenvug.pdf and <instdir>/doc/amssimug/amssimug.pdf
This does however require that you have the appropriate licences - either the AMS Simulator, Multi-mode simulator, or the Incisive AMS option (plus Incisive). To run within ADE, you need to be using IC5141 USR1 or later; the digital/mixed simulators come from the IUS stream (IUS56 is the latest).

There is also the spectreVerilog solution (this is a rather old approach, somewhat obsoleted by AMS Designer). This is a co-simulation approach, using spectre and Verilog-XL. You need to have verilog.vmx from an IUS (or LDV) stream in the path, and then you'd pick spectreVerilog as the simulator in ADE. This only works in ADE, and partitioning is done during netlisting. <instdir>/doc/mshelp/mshelp.pdf for more details.

AMS Designer can simulate Verilog, Verilog-A, Verilog-AMS, VHDL, VHDL-AMS, SPICE and Spectre netlists/models.
SpectreVerilog is constrained to Verilog, Verilog-A and schematic-based designs. There's limitations on where the "interface elements" (between the analog and digital domains) can be placed.

If you have a choice, I'd definitely recommend AMS Designer over SpectreVerilog.

Regards,

Andrew.