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Design Languages >> Verilog-AMS >> verilog-A model to check for pulse width
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Message started by rudy.talukder on Jan 12^th, 2006, 6:03pm

Title: verilog-A model to check for pulse width
Post by rudy.talukder on Jan 12^th, 2006, 6:03pm

Hi,
I am trying to write a verilog-A model for a circuit that will sense ‘a’ crossing below -17.99V and wait for 4us before the state changes from alive to dead. If it goes above -17.99V before the 4us the state should get restored to alive. If there is a glitch, it should again wait for 4us after the glitch goes away.

I am pasting the testcase.va file below:
//////////////////////////////////////////////////////////////////////////////////////////////////////

`include "discipline.h"
module testcase(a,b,c,d,e,f,dummy);
inout a,b,c,d,e,f,dummy;
electrical a,b,c,d,e,f,dummy;
real state,state2;
branch(b,c) device;
parameter real kill_start = 0.0;
parameter real alive = 1.0;
parameter real kill_end = 2.0 ;
parameter real dead = 3.0;
analog begin

@(initial_step) begin
state = alive; //alive state initially
state2 = alive;
end

V(dummy) <+ 0;

@(cross(V(a)+17.99,-1)) begin
state = kill_start; //Start of kill
end

if(state == kill_start) begin
V(dummy) <+ transition(2,4u); //4us is the minimum kill pulse width required
end

@(cross(V(a)+17.99,1)) begin
state2 = kill_end;
end

if((state == kill_start) && (V(dummy) >= 2)) begin //flip the state to dead
state = dead;
end

if((state == kill_start) && (state2 == kill_end)) begin //insufficient pulse width.flip the state back to alive
state = alive;
V(dummy) <+ transition(0,0u);
end

if(state == dead) begin
I(device) <+ (V(b)-V(c))/3185.558 + V(a)*(V(b)-V(c))*0.000095016666667;
end

if(state == alive) begin
I(device) <+ 0.00;
end

end
endmodule

////////////////////////////////////////////////////////////////////////////////

I am pasting the testcase.sp file below:
**********************************************
*
*.param HSIMVERILOGA="testcase.va"
.verilog testcase.va

vsource a gnd pwl(0u 0 1u 0 2u 1.1v 5u 1.1v 6u -18v 15u -18v 16u 0v 17u 1.1v 18u 1.1v 19u 5v )
Vsd e gnd pwl(0u 1.2v 1u 1.2v 2u 1.2v 5u 1.2v 6u 1.5v 15u 1.5v 15.5u 1.2v)
Vss d gnd pwl(0u 0 1u 0 2u 0 5u 0 6u 1.5v 15u 1.5v 15.5u 0v)
Vfc0 b gnd pwl(0u 0 1u 0 2u 0 5u 0 6u 1.5v 15u 1.5v 15.5u 0v)
Vfc1 c gnd pwl(0u 1.2v 1u 1.2v 2u 1.2v 5u 1.2v 6u 1.5v 15u 1.5v 15.5u 1.2v)
Vpw f gnd pwl(0u 1.2v 1u 1.2v 2u 1.2v 5u 1.2v 6u 1.5v 15u 1.5v 15.5u 1.2v)
vgnd gnd 0 0

.model testcase macro language=veriloga
y1 testcase a b c d e f dummy
*** Simulation Time
.tran 10n 60u

.plot TRAN v(*)
.plot TRAN i(*)
*.print v(*)
*.print i(*)
.end
****************************************************

I am simulating it on eldo. I am getting the following error:
'testcase.va', line 29: Error : Cannot use analog operators or analog event (@) statements inside if or analog event (@) blocks with non-constant conditions.

'testcase.va', line 43: Error : Cannot use analog operators or analog event (@) statements inside if or analog event (@) blocks with non-constant conditions.

testcase.va: module(s) testcase Failed With Errors.

ERROR 1102: VERILOG_A :COMPILER doesn't run successfully, "compiler error with "testcase.va" . stop"

Can someone help me in solving this?

Thanks,

Rudy

Title: Re: verilog-A model to check for pulse width
Post by jbdavid on Jan 13^th, 2006, 3:30am

You need to pick one transition statement and pass it a variable..
set that variable inside your conditions..

V(out) <+ transition(a,0 1n,1n);
@(initial_step(`tran) ) begin
state = 1;
a = 0; // alive
@(cross(V(in)+17, -1)) begin
a =0 ; //still alive
killX = $abstime + 14u; // this is when we kill it..
end
@(cross(V(in)+17, +1)) begin // if waiting to kill - return to alive state
if (!a ) killX = -1 ; // the timer will not activate..
end
@(timer(killX)) begin //
a = 1; // too bad - now we kill it..
end

Important thing is not to put the V(var)<+ transition(expr); inside an "if" block..
because the transition expression cannot be enabled and disabled.. or the simulator would loose track of when to start and stop the output..
so it has to be available (not inside if, then, case, else cross, timer initial or final steps.. )..
the variables in the expression are set inside those blocks..
HTH

Title: Re: verilog-A model to check for pulse width
Post by Ken Kundert on Jan 13^th, 2006, 8:42am

You might be able to get the behavior you describe by taking full advantage of the transition function as follows ...

Code:

@(cross(V(a)+17.99))
;
eventual_state = (V(a) > -17.99) ? alive : dead;
state = transition(eventual_state, 4u, 0);

state will transition to the desired value only after eventual_state has been stable for 4us.

-Ken