The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Modeling >> Semiconductor Devices >> MOS small signal output resistance model
https://designers-guide.org/forum/YaBB.pl?num=1137257914

Message started by steven on Jan 14^th, 2006, 9:07am

Title: MOS small signal output resistance model
Post by steven on Jan 14^th, 2006, 9:07am

Hello,

Given a MOS device at saturation, how to estimate the small signal output resistance rout? For example, if Id doubles, rout will decrease anti-proportionally (almost) according to approximation rout=Va/Id, with Va is related to geometry parameters and Vds. However, if taking a MOS device model for a simulation, the Gds hardly changes if Id changes. So it seems rout is not simply the relation was just outlined. Note that the simulation ensures the device is under saturation.

Thanks.

Title: Re: MOS small signal output resistance model
Post by Geoffrey_Coram on Jan 17^th, 2006, 6:41am

With some processes, 0.18u and below, the pocket or halo implant causes real trouble when trying to fit the output conductance curves. I've seen humps in the measured data. In that case, I don't think you'll find an easy approximation.

Title: Re: MOS small signal output resistance model
Post by steven on Jan 20^th, 2006, 3:41pm

Hi Geoffrey,

For circuit design purpose, I guess Rout is then assumed to be constant with respect to Id. In achieving enough voltage gain, we sometimes need Rout large. But it seems Rout is not well approximated by the pointed relation. Well, longer device can increase Rout.

Thanks for the information,
Steven

Title: Re: MOS small signal output resistance model
Post by pbs681 on Feb 17^th, 2006, 6:09pm

I have 1 question. Is there any relationship between rout and rds as we know that rout is the resistance looking at the output node when transistor is on, while rds is parasitic resistor. Sorry if I asked basic question. I just graduated and still new. Please help me.
Thanks