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Design >> Analog Design >> strange thing about my clock generator
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Message started by zychang on Jan 17^th, 2006, 11:45am

Title: strange thing about my clock generator
Post by zychang on Jan 17^th, 2006, 11:45am

Hi,

I found something really strange when I tested the clock generator for my switched-capacitor circuit. It was a two-phase non-overlaping clock generator. When I tested it seperatedly, everything seemed fine. But when I put it into the switched-capacitor circuit and simulated it in Spectre again, the clock wave seemed to need more time to settle (just like the time constant becomes bigger). It doesn't make sense to me because in both test circuits the input clock is the same. The only thing different is that, in the latter case, the clock signal goes to several transmission gates, while in the former case I just put output pins at the end of the clock signal. More, this phenomena becomes worse when I put the clock in a two-stage switched-capacitor circuit (S/H+Multiply-by-2). I just can't understand what is happening there. All suggestions are welcome.

Title: Re: strange thing about my clock generator
Post by Andrew Beckett on Jan 17^th, 2006, 8:46pm

Isn't this just a case of the gate capacitance of the transmission gates loading your clock generator? That's what it sounds like...

Regards,

Andrew.