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Simulators >> Circuit Simulators >> Clock generation when using PSS
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Message started by achim.graupner on Jan 20^th, 2006, 2:34am

Title: Clock generation when using PSS
Post by achim.graupner on Jan 20^th, 2006, 2:34am

Hi there,

I am designing an SC-ADC with some kind of sophisticated clocking. Thus I have about 10-20 clock signals.
Now I want to do an PSS/Pac/Pnoise analysis. Usually I use an automatically generated VerilogA-Model which provides all the required clock signals like in the following code:

@(timer(4*t_delay, t_period)) begin t_getph = vdd; end;
@(timer(4*t_delay+t_period/2, t_period)) begin t_getph = 0; end;
...
V(getph) <+ transition(t_getph , 0, 1n, 1n);

With this code PSS termiated with an error because of the hidden state in the model. If I however change the code to (see the ?: assignment in $transition)

@(timer(4*t_delay, t_period)) begin t_getph = 1; end;
@(timer(4*t_delay+t_period/2, t_period)) begin t_getph = 0; end;
...
V(getph) <+ transition(t_getph ?vdd:0, 0, 1n, 1n);

PSS runs without comment. The result however is not satisfactory. It seem as clock signal generated as above is not considered during the simulation.

Does someone has an idea how to automatically (at least to a large extent) generate a complex clock regime. The only idea I have so far is to use PWL-sources reading in some generated waveform. This however requires quite some effort (generating individual waveform-data, generate an VerilogA-view instanciating the PWL source etc.) and I am not quite sure whether this approach will work.

Any help is greatly appreciated.

Achim

Title: Re: Clock generation when using PSS
Post by Andrew Beckett on Jan 20^th, 2006, 3:33am

The second situation is still a hidden state, but obviously does not get noticed as being one. Please report this bug so that we can get it fixed.

You'll have to introduce some storage mechanism to keep track of the state (sorry, I don't have time at the moment to give an example). I suggest looking at Ken's paper on Hidden States in the Analysis part of this site (link at the top of the page).

Andrew.

Title: Re: Clock generation when using PSS
Post by achim.graupner on Jan 20^th, 2006, 4:26am

Hi Andrew,

I've already had a look on Ken's paper. Meanwhile I also tried to use PWL-sources, it does not work out. The PSS-analysis start shooting after the last event of the PWL-source.
It seems to me that the PSS is running only when
- periodic sources (vpulse, vsin, etc) or,
- in VerilogA the timer -event
are used to generate clocks for PSS. Does PSS only run successfully when the clock signals are periodic for an indefinite time?

Eventually I want to simulate a algorithmic ADC, so in a first clock cycle the ADC's input is read in, afterwards the ADC reads in its residual output for some cycles. It will be a hard thing to describe such a clock regime with peridocal sources/statements only.

Regards, achim

Title: Re: Clock generation when using PSS
Post by Geoffrey_Coram on Jan 20^th, 2006, 4:56am

Achim -
I have two thoughts for you:
1) I believe Spectre's PWL source now has a "repeat" parameter
2) I have a vague recollection of something in Spectre's Verilog-A for "instrumentation blocks" that relaxes the prohibition on hidden state. You may need Andrew to fill in more details on that one.

-Geoffrey

Title: Re: Clock generation when using PSS
Post by achim.graupner on Jan 20^th, 2006, 5:14am

Hee-hoo,
I found a solution to the problem: in Cadence IC5141 the following VerilogA attributes have been introduced:
(*instrument_module *) and (*ignore_state *)
It is said that SpectreRF can now simulate VverilogA modules with hidden states
-that act as sources and produce only outputs
-that act as probes and have only inputs
-that are used as local variables and are not true circuit states

(*instrument_module*)
module mul2_logic_driver

Now the check for hidden states is disabled. For me it works well.
(*igrnore state*) can be used before the declararation of a variable to prevent the hidden state error.

Thank you for your hints.
Happy PSS'ing

achim

Title: Re: Clock generation when using PSS
Post by Andrew Beckett on Jan 30^th, 2006, 2:16am

Disabling a hidden state by using these attributes is NOT valid if it is actually a real state variable. You'll most likely get the wrong results from PSS if you do this.

In both examples you originally posted, you seem to have hidden states which would affect the circuit results. From what you describe, the second example does not complain - but it should.

Regards,

Andrew.

Title: Re: Clock generation when using PSS
Post by achim.graupner on Jan 30^th, 2006, 11:28pm

Hi Andrew,

as stated at the begin of the topic all I want to do is to generate periodic clocks signals with some certain timing between each other. Conventionally this is done using pulse-sources. THis however is to complicated for me. So I now use a output-only block doing nothing but generating periodic clock signals. I am aware that I have to assure that the same periodicy is used for PSS analysis as the periodicy is not automatically detected as when using pulse sources,
I tried this using a simple sample-and-hold device and compared the results with a testbench where pulse sources have been used. The results are indentical. SO I suppose this method for generating clocks can be used.

Regards, achim