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Design >> Mixed-Signal Design >> multi-input digital adder
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Message started by vivkr on Jan 22nd, 2006, 2:58am

Title: multi-input digital adder
Post by vivkr on Jan 22nd, 2006, 2:58am

Hi,

I would like to know how one can make >=3-input full adders. I have 2-input
full adders available, but I cannot figure out a way. I thought this was quite simple
but now I don't see how I can get a 3-bit word which would result from adding
3 inputs and a carry bit. Perhaps I could make a dedicated block by using the K-map
but I think this is not the right way to do it.

Perhaps the problem is simple to some of you and I would be grateful if someone
could show me an example where 2-input FAs are used to make a 3-input FA.

Regards
Vivek

Title: Re: multi-input digital adder
Post by huber on Jan 25th, 2006, 8:49am

Hi vivkr-
You can always just cascade the full adder cells in a Wallace tree.  This is the textbook way of adding a large number of partial products in multipliers.  You'll need 3 FAs, or 1 FA and 2 HAs.
-Dan

Title: Re: multi-input digital adder
Post by vivkr on Jan 31st, 2006, 11:25pm

Thanks Dan !!!

This should help. I was also trying to see if I could optimize speed by directly building a 3-input
adder, but I think it is easier for me to use your suggestion.

Regards
Vivek

Title: Re: multi-input digital adder
Post by chase.ng on Mar 13th, 2006, 10:22am

Hi,

A 3-bit full adder is possible just by deriving the circuit from the boolean equation, but that will have more than 2 transistors stack-up on top of each other, which will eventually slowing down the adder instead of speeding them up. This is especially true in high speed domino style tree adder with tight timing window, unless the adder is to be design in SOI technology where body effect is not a concern.

Chase

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