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Design >> Analog Design >> minimizing variation in latch turn-on delay
https://designers-guide.org/forum/YaBB.pl?num=1138116785

Message started by vivkr on Jan 24^th, 2006, 7:42am

Title: minimizing variation in latch turn-on delay
Post by vivkr on Jan 24^th, 2006, 7:42am

Hi,

I am using a simple latch with back-back connected load devices providing +ve feedback
on a diff pair, and a clamping diode.

This latch has a turn-on delay which is dependent on the input common-mode voltage
but the turn-off delay is relatively constant.

Does anyone have any suggestions on how the variation may be minimized?

Thanks
Vivek

Title: Re: minimizing variation in latch turn-on delay
Post by steven on Feb 5^th, 2006, 8:14am

vivkr wrote on Jan 24^th, 2006, 7:42am:

Hi Vivek,

So your circuit is a comparator with preamp and latch, right? Have you figured out what to improve the turn-on delay? Does the delay come from the first stage? Because the latch's input is a larger signal.

Regards,
Steven

Title: Re: minimizing variation in latch turn-on delay
Post by vivkr on Feb 7^th, 2006, 3:29am

Hi Steven,

I only have one stage in my comparator. As for the delay variation, normally you have to balance
the PMOS and NMOS devices to adjust the delay skew. In my case, there was skew even despite this.

The reason was that the tail current source (I have a preamp only) had too little headroom during the
large swings. I fixed this by adjusting device sizes and the variation went away.

Normally, this should not have caused a problem if there are complementary inputs on the latch. In my
case, one input was fixed and the other was changing. Hence, there was an inherent asymmetry which was
worsened when the input fall too low, causing small Vds across the tail current, and modulating it.

In a fully differential scenario, the modulation is same in both cases and no net variation is seen.

Regards
Vivek

Title: Re: minimizing variation in latch turn-on delay
Post by steven on Feb 7^th, 2006, 11:24am

Hi Vivek,

After reading your reply, I realize I have over-complicated the situation. I thought that delay skew might come from either overdrive or what you tried to make a rail-to-rail input comparator.

I guess you have used NMOS as the input differential pair. What if changing to PMOS differential pair (the latch stage changes too)?

Regards,
Steven