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Design >> Analog Design >> Definition of a 2.5v nmos
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Message started by MTXamp on Jan 28^th, 2006, 1:01am

Title: Definition of a 2.5v nmos
Post by MTXamp on Jan 28^th, 2006, 1:01am

Hi

According to the documentations, my current pdk provides 2.5V nmos and pmos transistors. May I know if this 2.5V is refering to the breakdown voltage of the mos transistors? Meaning that no more than 2.5V should be applied across Vds? Thank you. :)

It was not clearly stated in the pdk documentation. :(

Best regards

Title: Re: Definition of a 2.5v nmos
Post by Paul on Jan 29^th, 2006, 12:43pm

Hi,

the device voltage determines the normal regime of operation of the transistor, i.e. a 2.5V device is supposed to be operated under supply voltages of 2.5V±10%. It will certainly not break down when being subject to a somewhat larger gate or drain-source voltage for some time, but this is not recommended for reliable operation over a longer time scale. You can have a look at the reliability information usually included in the design kits for more information on ageing under stress.

Some people also use devices under supply voltages exceeding the nominal value and make sure that each individual device isn't subject to a GB, GS, GD or DS voltage exceeding the nominal value. This practice is considered arguable by others.

Paul