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Design >> RF Design >> VCO & Buffer
https://designers-guide.org/forum/YaBB.pl?num=1138502368

Message started by hrkhari on Jan 28^th, 2006, 6:48pm

Title: VCO & Buffer
Post by hrkhari on Jan 28^th, 2006, 6:48pm

Hi Guys:

Attached is the buffer I had used in isolating the ,3.8GHz-3.1GHz,VCO output. I find that this buffer provides comparable good output swing, to the ratio of power consumption in comparison with the common source follower stage. I'm using a resistive degeneration load, with respect to the current source. The questions are:

1. Does this degenerative load needs to be 50 Ohms, currently it ranges to 500 Ohms in my design?

2. The find that the phase noise of the VCO increased due to the increased number of transistors, does one take into account of the phase noise of the core circuitry in a VCO design or the whole buffer and VCO integration?

3. I find that for both of the types of the buffer stage the output is attenuated around 50mV from the input, I can't seem to boost the gain to unity or larger, is this quite normal ?

4. Finally in measuring the S21 and S12 characteristic of the buffer, I understand I need to terminate the input and output with ports, where output port is 50 Ohms terminated, the input of this buffer comes from a autonomous VCO, How much impedance shall I terminate in the input?.

I would really appreciate your kind help in resolving this issues. Thanks in advance

Rgds

Title: Re: VCO & Buffer
Post by mobil on Aug 22^nd, 2006, 6:27pm

due to the VCO ouput is a large signal, so to match the buffer is not the same definition of small signal like PA or LNA, especially when you testing the output impedence of a VCO, it should be a variable, I think.

This link they talked about 'Large Signal S-Parameters' may be useful for your question:
http://www.designers-guide.org/Forum/YaBB.pl?num=1031864062

Title: Re: VCO & Buffer
Post by loose-electron on Aug 23^rd, 2006, 7:55am

Any source follower (in this case PMOS) will be a bit lossy at high frequencies.

Unusual architecture - the gate of the top transistor does not really seem to have a well defined operating point?

If this is an AC coupled system, why not just use an NMOS source follower?

Also, are you including some estimated parasitics at the moment? At 4Ghz (more or less) this is going to affect things in a big way.

Jerry

Title: Re: VCO & Buffer
Post by RFICInDaHouse on Oct 9^th, 2006, 7:30pm

hrkhari,

The follower you are using is similar, in principle, to the "super source follower" configuration. Consult Gray and Meyer book for more info.

1_ The output impedance of the buffer should be close to 50 ohms. The PMOS load (M2) is creating a feedback to give more current at the output for a minute voltage swing. use a single port element to measure the s-parameter at the output node.

2_ Idealy, the phase noise should not be significantly affected by the buffer or even affected at all. Is transistor M1 entering the cutt-off region for a fraction of the oscillation period. If so, that might generate AM-to-PM noise.

3_ It's even quite normal to got more attenuation.

4_ The input of the buffer should present the minimum capacitance loading to the tank circuit. I usually run a dc analysis and calculate the gate capacitance.