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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Comparator resolution https://designers-guide.org/forum/YaBB.pl?num=1139452656 Message started by steven on Feb 8th, 2006, 6:46pm |
Title: Comparator resolution Post by steven on Feb 8th, 2006, 6:46pm Hi, I have a question on comparator's resolution. The comparator resolution is related to the offset voltage. Without offset compensation, the offset voltage is proportional to Vt variance and proportional to Vov. With offset compensation, the offset voltage can be further reduced. In both of these two cases, how to justify the comparator resolution due to fabrication process variances such as Vt? Or is it simply not possible without actual measurements? Thanks, Steven |
Title: Re: Comparator resolution Post by huber on Feb 10th, 2006, 8:53am The main source of comparator offset is threshold voltage mismatch, but dynamic issues (such as mismatch in load capacitance) tend to result in larger offsets than you would expect. There was a paper presented on Tuesday at ISSCC that implemented tunable load capacitance to compensate for comparator offset; very cool stuff. If you have good mismatch data then you should be able to simulate comparator mismatch accurately. Not sure what you mean by "how to justify the comparator resolution". -Dan |
Title: Re: Comparator resolution Post by steven on Feb 17th, 2006, 12:25pm huber wrote on Feb 10th, 2006, 8:53am:
Hi Dan, Ok, I see. When I said "how to justify the comparator resolution", I was thinking to justify the resolution analytically rather than simulation or measurement. Thanks for clearing up. Steven |
Title: Re: Comparator resolution Post by river on Feb 19th, 2006, 8:21pm huber wrote on Feb 10th, 2006, 8:53am:
hi, huber will you please tell me the title of the paper, I am really interested in it. thanks in advance. river |
Title: Re: Comparator resolution Post by huber on Feb 20th, 2006, 10:26am Hi river- The paper was presented in Session 31: Very High Speed ADCs and DACs. The title is "A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process". The authors are G. Van der Plas, S. Decoutere, and S. Donnay. Unfortunately I don't think the 2006 proceedings are online yet, so you'll either have to wait or find someone with a paper copy. Basically they used a sense-amp-sytle latch loaded with banks of PMOS gate caps. Each cap has a source/drain terminal that is controlled by a programming bit, which determines if the cap has an inversion layer or not. -Dan |
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