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Design >> Analog Design >> variation of bandgap output voltage
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Message started by jcpu2006 on Mar 12^th, 2006, 10:22pm

Title: variation of bandgap output voltage
Post by jcpu2006 on Mar 12^th, 2006, 10:22pm

need help regarding variation of bandgap output voltage:

Process used: standard CMOS,
BJT device: parasitic vertical, ratio=12:2
architecture: bandgap with opamp, opamp gain ~ 40dB, loop AC stable
measurement result: +/-70mV standard deviation, mean-value=1.2V @room temperature,
question:
need help / reference material for a systematic method to reduce with the variation,
I wonder if the major variation come from the BJT process control??
Does someone has experience upon this?
:-?

Title: Re: variation of bandgap output voltage
Post by chase.ng on Mar 13^th, 2006, 8:43am

Hi,

How about increasing the opamp gain, and try to increase the size of the opamp input differential pair to reduce the random offset? I think opamp offset will probably contribute major deviations to the bandgap output. Try Razavi's book on how to reduce effects of opamp offset in bandgap.

BTW, I am just curious, how is your monte carlo simulation results correlate with your measurement results?

Chase

Title: Re: variation of bandgap output voltage
Post by Paul on Mar 13^th, 2006, 12:35pm

Hi,

you give a standard deviation of ±70mV on Vbg, but you don't say what is the number of measurements and especially what is the variable.
Are there several measurements on the same die in a timely manner, in which case the reason would be noise/drift?
Are the measurements performed on different dies, in which case the problem is process variations (device mismatch, opamp gain and offset, ...)
Are the measurements performed while sweeping temperature, in which case your variations are due to the higher temperature coefficients and opamp gain and offset variations?

In any case 40dB of DC gain in the opamp seems low to me as already stated by chase. You can also expect the DC gain to change a little over temperature.

Based your answers to the above questions it should be possible to give further indications on the possible sources.

Paul

Title: Re: variation of bandgap output voltage
Post by RobG on Mar 17^th, 2006, 10:06pm

I've been doing bandgaps for quite some time. Variation is generally caused by mismatches, although you can mess up a bandgap dozens of ways. Most likely culprit is op-amp offset, which gets gained up by the resistor ratio (probably about 12 in your case). An opamp offset of just 6mV would give you 72mV at the output if the gain is 12... The second likely culprit is resistor mismatch.

I don't think low opamp gain is causing variance, but it will likely cause other problems (e.g. low power supply rejection, etc.).

There was a paper at 2004 CICC on a systematic way to reduce the effects of mismatches by optimizing the areas allocated to the components by Gregoire: http://ieeexplore.ieee.org/iel5/9389/29800/01358908.pdf?tp=&arnumber=1358908&isnumber=29800

Title: Re: variation of bandgap output voltage
Post by jcpu2006 on Mar 20^th, 2006, 1:19am

Dear Sir:

Allow me to answer Paul first: It's the second case:
"the measurements performed on different dies, in which case the problem is process variations (device mismatch, opamp gain and offset, ...)"
upon 100 samples at room temperature.

Secondly, please refer to the attachment:
The gain is not that high, and what we have for comparator input stage is W/L=10u/10u m=8 pmos pair.
I'll be back with some monte carlo analysis results.

Thanks in advance,

Title: Re: variation of bandgap output voltage
Post by raul on Mar 20^th, 2006, 12:05pm

To add to the comments above. Have you checked if you have high impact ionization currents in your CMOS process affecting your bandgap's output voltage? This would be seen as curent going from drain to bulk (idb) in your .op analysis. Check at maximum supply and -40 Celsius to see worst case results.
No matter how high the open loop gain of your opamp, high impact ionization current in your transistors will cause your PSRR to look awful since these currents generate an offset proportional to power supply. The only solution here is to sub-regulate your power supply inside the IC or use a technology that doesn't have bad impact ionization performance. Good luck.

Title: Re: variation of bandgap output voltage
Post by jcpu2006 on Mar 26^th, 2006, 8:17pm

Dear Raul:

Those data of chip to chip variation are obtained at same VDD.

I could not understand why this variation has something to do with PSRR.

Thanks

Title: Re: variation of bandgap output voltage
Post by raul on Mar 26^th, 2006, 9:22pm

if indeed your problem is related to impact ionization currents creating errors in your reference(nothing you've posted implies that this is the case or rules it out so this is only something that you should check). higher supply voltages would increase the Vds of some of the transistors in your reference and that would increase the error introduced to your reference voltage at the output through the idb currents. This is why i mention PSRR, because it's an error that depends on supply voltage. higher supply voltages result in higher errors. good luck.