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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> adding redundancy to successive-approximation ADCs https://designers-guide.org/forum/YaBB.pl?num=1143537884 Message started by vivkr on Mar 28th, 2006, 1:24am |
Title: adding redundancy to successive-approximation ADCs Post by vivkr on Mar 28th, 2006, 1:24am Hi, I am wondering if one could add some sort of redundancy to conventional hybrid successive-approximation ADCs (using R-ladder + binary-weighted cap array) as shown in Allen & Holberg/Johns&Martin. The offset of the comparator is very critical here. Although one may use offset cancellation by closing the loop around the comparator, this necessarily reduces the speed of the circuit, especially if one wants to sample a fast input signal. Any references or suggestions would be very welcome. Regards Vivek |
Title: Re: adding redundancy to successive-approximation Post by sheldon on Mar 28th, 2006, 8:14am Vivkr, Can't you auto-zero the comparator while sampling the input signal? You don't need to auto-zero the entire comparator, you only need to auto-zero the first few stages. Or you can ping-pong multiple ADCs, this is approach is used to build high speed pipeline ADC. BTW, here are a few papers on sub-radix 2 successive approximation ADC design. Design and Modeling of a 16-bit 1.5MSPS Successive Approximation ADC with Non-binary Capacitor Array, GLSVLSI ’03, April 28-29, 2003, A 12-bit ADC Successive-Approximation-Type with Digital Error Correction, Kanti Bacrania, JSSC, Dec. 1986 Best Regards, Art Schaldenbrand |
Title: Re: adding redundancy to successive-approximation Post by vivkr on Mar 29th, 2006, 11:00pm Hi Sheldon, Thanks for the tip. I can use this. However, I considered another possibility that would involve measuring the offset and storing it digitally on-chip. This would then allow self correction. However, resetting the first stage as you suggest sounds simpler to me. However, I would really be interested in knowing if one can add redundancy to the SAR ADC in a similar fashion as one does for pipelined of cyclic ADCs where the 1.5-bit stage relaxes the performance constraints and accuracy requirements of the comparator itself. In the absence of any gain in conventional SAR ADCs, I don't see offhand how one could go about adding redundancy of this kind, but perhaps someone has an idea. Regards Vivek |
Title: Re: adding redundancy to successive-approximation Post by RobG on Mar 30th, 2006, 9:26am Vivkr - I don't know if this adds anything to what Sheldon said, but I believe redundancy is the intent of the SAR presented at ISSCC 2006 by Chen ("A 6b 600MS/S 5.3mW..."). It was paper 31.5 on pages 574-575. From the paper: A non-binary capacitor array is used that requires 7 comparison cycles from 6b resolution, which allows extra tolerance for dynamic error through overlapped searching range. The author credits the idea to: Kuttner, "A 1.2V 10b...," ISSCC Dig tech papers, pp 176-177, Feb 2002. If you sub out the offset digitally, be aware that it will change over temp. A rough number would be 5-10uV/C, but you can make that better (or worse!) if you know what you are doing. Hope this helps... |
Title: Re: adding redundancy to successive-approximation Post by Andrew Beckett on Mar 31st, 2006, 2:35am I am joint author of a patent (US 5870052) for a "redundant" SAR method. It's discussed in the following paper: http://ieeexplore.ieee.org/iel5/9916/31525/01470867.pdf?isnumber=31525&prod=CNF&arnumber=1470867&arSt=+76&ared=+79&arAuthor=+Schofield%2C+W.G.%3B++Dedic%2C+I.J.%3B++Kemp%2C+A.K. which was written by some of my former colleagues after I'd moved from Fujitsu to Cadence. Regards, Andrew. |
Title: Re: adding redundancy to successive-approximation Post by vivkr on Mar 31st, 2006, 3:34am Hi RobG, Thanks for the links. I ran through Kuttner's paper and it appears to be exactly what I was looking for. Now, I should try to look at it in more detail to see if I understand the correction scheme. Regards Vivek |
Title: Re: adding redundancy to successive-approximation Post by vivkr on Mar 31st, 2006, 3:44am Hi Andrew, I guess you posted a few seconds before me. Thanks for the link. Indeed, this approach looks quite interesting as well. I think with the links sent by you and Rob, I will be able to figure out a way of getting redundancy into my scheme. However, I don't think I will be able to use either your scheme or Kuttner's as yours is patented, and the same would probably hold for Kuttner's. Regards Vivek |
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