The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> some layout questions in mixed-signal design https://designers-guide.org/forum/YaBB.pl?num=1143561678 Message started by zychang on Mar 28th, 2006, 8:01am |
Title: some layout questions in mixed-signal design Post by zychang on Mar 28th, 2006, 8:01am Hi all, I'm new to the analog/mixed-signal design, esp. in the sense of layout, and I just found some questions which have annoyed me these days. Any suggestions will be appreciated. In my design, there is an opamp, which is supplied between plus/minus 3.3V, a bandgap circuit which is supplied between positive supply, Vdd, and gnd, and some digital logic circuits also supplied between positive supply and gnd. First, I built them seperatedly and they all pass the DRC & LVS check. Then, when I tried to put the opamp and the logic together and did the DRC check, it came up with some errors saying short between Vssa and gnd! and short between Vdda and vdd!. I think the problem could be the p-substrate/nwell contacts because I have put them to both of the two parts. My question now is 1) how to put the analog and digital circuits together when they have different power supplies and do the DRC and LVS check? what do peope usually do in this topic, and 2) would there be any concerns i should be aware of if two analog blocks using different supplies are put together (like the bandgap circuit and the opamp in this work) coz i havn't moved on to that part yet. looking forward to your opions Mike |
Title: Re: some layout questions in mixed-signal design Post by vivkr on Mar 29th, 2006, 1:05am Hi Mike, If you are using different supplies for different blocks, the first and most important thing you need to check for is whether you can actually fabricate such a design. If you are using a standard digital CMOS process, it may not be possible at all as there is only the global p-substrate for creating NMOS devices, and an N-well for creating the PMOS devices. You will need a slightly enhanced CMOS process where you have a deep N-well available. In this deep N-well, you will then need to create a P-well which acts as the bulk for one part of your circuit, whereas the remaining part is placed directly in the global substrate. Typically, the block operating from the most -ve supply is placed in the substrate and this -ve supply is then tied to the substrate. Important issues to look for: 1. Potential latchup action through parasitic bipolar action. 2. The order in which various supplied are turned on. Regards Vivek |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |