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Design >> Analog Design >> First stage gain calculation
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Message started by MTXamp on Apr 1^st, 2006, 5:24pm

Title: First stage gain calculation
Post by MTXamp on Apr 1^st, 2006, 5:24pm

Hi

I am trying to figure out how to calculate the first stage gain of the opamp shown in the lower portion of the attached picture. The opamp is similar to that of a folded cascode type but due to the presence of M10 and M11, I am not sure how to calculate the output resistance (and hence gain) of the first stage.

May I have some hints please? Thank you.

Best regards

Title: Re: First stage gain calculation
Post by RobG on Apr 4^th, 2006, 8:08pm

If memory serves me well, M10 and M11 affect the gain very little. Treat them like they are ideal level shifters; that is, the outut impedance is simply Ro7||Ro4.

Title: Re: First stage gain calculation
Post by Paul on Apr 5^th, 2006, 1:05pm

Hi,

this topology has been published in
A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries
Hogervorst, R.; Tero, J.P.; Eschauzier, R.G.H.; Huijsing, J.H.;
Solid-State Circuits, IEEE Journal of
Volume 29, Issue 12, Dec. 1994 Page(s):1505 - 1513

This topology provides class-AB operation of the output stage at a power-supply independent (and first-order process independent) quiescent current. Indeed, the use of a simple inverter in an integrated op-amp is usually prohibitive due to the large power consumption variations with process, temperature and supply.

As the amplifier output voltage is not affected actively, the amplifier gain is not modified. However, I am not exactly sure how M5 (added for symmetry?) in the other FC branch affects the amplifier behavior.

Hope this helps

Paul