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Measurements >> Phase Noise and Jitter Measurements >> Is there a better way to sim PLL jitter transfer?
https://designers-guide.org/forum/YaBB.pl?num=1144220310

Message started by bluestatic on Apr 4^th, 2006, 11:58pm

Title: Is there a better way to sim PLL jitter transfer?
Post by bluestatic on Apr 4^th, 2006, 11:58pm

Can anyone tell met that in general case, how was a PLL jitter transfer sim was performed. The way I'm currently thinking is :

1. modulate the input ref clock with a jitter frequecy Fj, and set the max input jittter peaking to be 0.1UI of input reference clock
2. do transient sim to get PLL output clock waveform for cetain time, use script to calculte the output clock pk-to-pk jitter and divide it by input jitter peaking (0.1UI of input reference clock)
3. vary Fj from 0 to 100M in 5M step, plot the result

In above simulation, only behavioral model of PLL can be used since it take too long to simulate with schematic.

Is it going to work? or any problem with method?