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Simulators >> RF Simulators >> unbelievable pnoise results of chained buffers
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Message started by rlim on Apr 5^th, 2006, 5:46pm

Title: unbelievable pnoise results of chained buffers
Post by rlim on Apr 5^th, 2006, 5:46pm

I have a cml buffer and a cml2cmos converter chained together. And with pnoise set to 'sources' with an ideal input sine wave, and looking at phase noise at both the cml buffer output and the cml2cmos converter output, pnoise reports a 5-6db lower noise @1MHz offset at the output of the cml2cmos converter! Is this even possible? I know that the cml2cmos converter is not bandlimiting since the input frequency is in the 100MHz range. My hunch is that setting pnoise to 'sources' is not the correct way but I don't know why. The documentation explains 'sources' as a time-averaged analysis but what does that mean? Does it also mean that time-averaged analysis should not be applied to cmos outputs since we only care about noise at the transitions? Can someone please straighten me out?

Thanks in advance,
Richard

Title: Re: unbelievable pnoise results of chained buffers
Post by Visjnoe on Apr 7^th, 2006, 12:13am

Hi Richard,

I believe the phase noise/jitter performance can become better when sending your signal through a CML + CML2CMOS converter structure: no statements can be made in general here however!

On the one hand, these blocks obviously add additional noise (e.g. thermal noise).
On the other hand, the 'gain' of your CML2CMOS converter can make the edges of your signal more steep,
effectively improving the jitter performance of your signal.

Kind Regards

Peter