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Design >> Mixed-Signal Design >> Negative setup time and postive hold time?
https://designers-guide.org/forum/YaBB.pl?num=1144973286

Message started by sylak on Apr 13^th, 2006, 5:08pm

Title: Negative setup time and postive hold time?
Post by sylak on Apr 13^th, 2006, 5:08pm

I came across a differential FF ( had data /datab and out/outb)which has a -ve setup time and +ve hold time. This has me throughly confused. Supposed the setup time is -10ps and hod time is 30ps ,and clock starts at 0s-does this mean in the time from the 0 to 30ps if there is a transition on the data , the FF fails?.. How would you distingusih between setup violation and a hold violation?

Moreover if the data transistion is from 0 to 1 or 1 to 0 how would this affect the setup/hold time?

Would appreciate if anyone throws light on this....?

Title: Re: Negative setup time and postive hold time?
Post by jbdavid on Apr 15^th, 2006, 2:11pm

I would interpret that spec this way:
the data must be valid from 10ps to 30ps after the clock edge ..

standard interp is that setup time is the time before the clock edge that the data must be stable for a clean read..
if negative, that would mean you have 10ps AFTER the clock where the data would be allowed to change..
and any change AFTER 30ps will be ignored until the next clock..

jbd