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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> text file for DAC input~ https://designers-guide.org/forum/YaBB.pl?num=1145343007 Message started by YiLi on Apr 17th, 2006, 11:50pm |
Title: text file for DAC input~ Post by YiLi on Apr 17th, 2006, 11:50pm Hi all, I am new to here, and I am doing some analog and mix-mode design now. I have a 12 bits DAC circuit(on spectre), and it needs a input for the simulation. However, the simulation data from the interpolator (previous stage) is generated by ModelSim, and its a text file with 0s and 1s~ Here is my question, 1. Can Spectre read text file as its input? or, 2. Do I need to build a VerilogAMS model to read the file and then generate 12 output signal for DAC as its input? if so, how can I do that? Thank your for your patience~ YiLi |
Title: Re: text file for DAC input~ Post by YiLi on Apr 19th, 2006, 9:06pm can any one help?? or should I just build interpolator in to a symbol with verilog code and simulate with SpectreVerilog?? |
Title: Re: text file for DAC input~ Post by Andrew Beckett on Apr 19th, 2006, 11:04pm It depends on the input format. spectre can read vcd (Verilog Change Dump) format files these days (see the documentation for more details - you'll need a recent MMSIM60 version for this). Also, you could write a verilog-a model using $fopen()/$fscanf() to read the file. Or if you can convert the data to a set of piece-wise-linear voltage versus time files, you could just use vsource components with the type set to pwl. Regards, Andrew. |
Title: Re: text file for DAC input~ Post by YiLi on Apr 20th, 2006, 7:19pm Hi Andrew~!! Thanks for your kindly reply~!! but, I still have some questions: What is MMSIM60? is that means I can't read VCD format file in IC5141? Sorry, I can't attache the file here, so I just put some rows... 00000000000000 00000011111100 00000111100000 00001010010101 00001100001010 00001100110011 00001100001101 00001010011011 I guess I will thry the $fopen()/$fscanf() to read the file... (I thought verilogA does not contain fscanf?) change the file to PWL seems too complecated... Thank you~ Best regards, YiLi |
Title: Re: text file for DAC input~ Post by YiLi on Apr 20th, 2006, 8:33pm sorry, one more question... I've tried to use integer infile; integer vd[13:0]; infile = $fopen("file.dat", "r"); $fscanf(infile, "%d", vd[13:0]); however, I want the outputs to be 14 electrical pins, and the vd[13:0] contains only integer! so I can't transfer the digital 0100110101 to a voltage output~~ V(vd1) <+ transition( vd[13], tdel, trise, tfall ); how can I do now? please help me~~ Thank you~ YiLi |
Title: Re: text file for DAC input~ Post by jbdavid on Apr 21st, 2006, 12:38am with IC5141 there is a library called bmslib it has a few verilog-a models in it.. a helpful one in thls case is busset8 - to show you how to take integer -> 8 bits out.. (thats tested and what folowes isn't . what you want to do is read the integer from the file then set 14 outputs based on that integer.. module file2source (out, clk, gnd); output [13:0] out; electrical [13:0] out; input clk; electrical clk; inout gnd; electrical gnd; parameter vhi = 1.5; parameter vlo = 0; parameter tr = 20p; parameter tf = 20p; integer vd[26:0]; // number of samples to read from the file if doing it all at once? integer vd; // holds the entire integer value if reading from the file until its empty integer infile; analog begin @(initial_step) begin infile = $fopen("file.dat", "r"); $fscanf(infile, "%d", vd); // only reading 1 integer (integer has 32 bits) end @(cross(V(clk,gnd)-0.5*Vhi, 1)) begin // posedge $fscanf(infile, "%d", vd); // only reading 1 integer (integer has 32 bits) // what if EOF? end generate i (13, 0) begin V(out[i],gnd) <+ transition((vd & 1<<i)?vhi: vlo, 0, tr, tf); end // note this form of generate statement is deprecated syntax.. but still works in 5141.. and mmsim6.. there is a newer form of the syntax in the AMS2.0 LRM, but last time I tried that I think it didn't work in 5.0.33 (now in EOL - but I still have to support it for a while yet.. so I'm waiting a little longer before going to the new syntax.. you may be luckier.. ------------------------------- OR you could run spectreVerilog OR you could run AMS designer, and write your DAC to use Logic input values (some examples of that in bmslib too.. but AMSD takes 3 tokens.. G'luck! jbd |
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