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Design >> Analog Design >> error amplifier specs in ldo
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Message started by chethan on Apr 18^th, 2006, 6:19am

Title: error amplifier specs in ldo
Post by chethan on Apr 18^th, 2006, 6:19am

Hi all,
I am supposed to design an LDO with 1.5V ( Fixed) output and a max current of 150mA. How should i find out what gain I need for my error amplifier. How can i decide upon the specifications for error amplifier like GBW, slewrate etc. can someone help me on this. any materials regarding the same would be very helpful.

Title: Re: error amplifier specs in ldo
Post by Visjnoe on Apr 18^th, 2006, 10:59am

Hi,

Here's a link to Rincon-Mora's website, containing lots of stuff about CMOS LDO's:
http://users.ece.gatech.edu/rincon-mora/

Kind Regards

Peter

Title: Re: error amplifier specs in ldo
Post by raul on May 2^nd, 2006, 6:34pm

Your gain is set by your line regulation(PSRR at 0Hz) or your load regulation, whichever is worse. Try the slow P or weak P corner at maximum temperature and this will tell you the worst case gain for a weak power device.
The bandwidth is set by either the max Iq available or your PSRR over frequency requirement(Audio usually requires 60 dB @20KHz) since you need to have loop gain at the frequency you want rejection. There are all sort of tricks; dynamic biasing of certain key blocks in the LDO proportional to load current, ways to compensate the loop, interesting architectures for any load capacitor stability, etc... The smaller your load capacitor, the faster your linear loop needs to be in order to avoid the output voltage from dropping, dynamic biasing usually helps here a lot.

Title: Re: error amplifier specs in ldo
Post by grosser on May 5^th, 2006, 10:59am

chethan wrote on Apr 18^th, 2006, 6:19am:

in prof. Mora's publications you have formulas, which relates GBW to time response, gain to load regulation...

there is an article:

Relationship between frequency response and settling time of operational amplifiers- google it

regards