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Simulators >> Circuit Simulators >> Post Layout Simulation
https://designers-guide.org/forum/YaBB.pl?num=1145367413

Message started by chase.ng on Apr 18^th, 2006, 6:36am

Title: Post Layout Simulation
Post by chase.ng on Apr 18^th, 2006, 6:36am

Hi all,

Just want to know what is the best way to run the post layout simulation. Normally when then first layout comes out, the parasitic will cause the specs to deviate from prelayout simulation, if we want to retune the circuit, do we change the schematic, and then the layout, re-extract and then run the post layout simulation again? Is there any other option? So that the specs will converge faster.

Thank you.
Chase

Title: Re: Post Layout Simulation
Post by achim.graupner on Apr 18^th, 2006, 7:16am

Hi Chase, dear all,

I in generally do the following: I do an extraction without parasitics and check the simulation rsults. Normally, there should be no differences. If so, the check the extracted parameters vs. the device parameters. There migth be differences in area/perimeter entailing those differences. Also the capacitances of resistors and capacitors to substrate are often not well modeled. If you have a well maintaned device lib in gerneral there should be no differences. If you have made poor assumtions in your schematic plenty of work is waiting for you :-|

Once the firsr step has been successful I enable the parasitic capacitances. Then frequently parameter changes of the circuit parameters can be observed. I then try to find out which capacitances are the reason for the differences. Here I use some scripting on the netlist to automatically remove certain parasitic capacitors (i.e. all capacitors connected to the circuit's input, all capacitors connected to the reference input etc.). Usually quite quickly the sensitive nodes and a handful of disturbing capacitors can be identified and hopefully removed in the layout.

If you use Cadnece the is a nice but rarely known feature available:
1. name all nets in the schematic
2. do an extraction / LVS
3. in the command line type: lvsbx
4. now create an analogExtraced
5. in the analogExtracted view nets have the same name as in yhe schemtic. So easily nets can be identified (and pcapacitors connected to those nets automatically be removed)

Finally you may enable parasitic resistors too. Here so far I never encountered any problems.

Regards, achim

Title: Re: Post Layout Simulation
Post by ACWWong on Apr 19^th, 2006, 6:51am

Generally most designers, given some experience, think carefully of the physical design (layout)when designing at the schematic stage. This is especially true in RFIC design.
For example, designing an LNA in the schematic stage should have more gain and better NF than specification, knowing that the layout will tend to degrade both these figures of merit. The estimation of the parasitics (metal R & C, corsstalk etc.) in advance of the full alyout can be estimated from the process data or with a trial layout, and salient/sensitive net parasictics can inserted into the schematic as parasitic devices to help the schematic design get close first time.

chase.ng wrote on Apr 18^th, 2006, 6:36am:

Title: Re: Post Layout Simulation
Post by chase.ng on Apr 19^th, 2006, 2:10pm

Hello all,

If the post layout simulation results do get worse than the prelayout results, is there anyway to effectively estimate the changes need to make on the schematic before actually changing the layout?

Thanks and Regards,
Chase

Title: Re: Post Layout Simulation
Post by ACWWong on Apr 19^th, 2006, 2:33pm

pre-emption is better than cure, so trial layouts and layout parasitic estmination by calculations at the schematic design stage can save time.
If after post-layout simulation you circuit/layout shows you have problems, it very much depends on your circuit as to what steps are needed.... the designer should really know what nets/nodes are critical from the aspect of layout parasitics..
Anyway as a tool for finding which parts of the layout are causing problems, you can examine the post-layout netlist (which inlcudes the extracted parasitic RC) and back annotate salient parasitics onto the schematic. This is particularly useful for seeing systematic parasitic mismatch in differential circuits for example.