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Design Languages >> Verilog-AMS >> Simple question about output assignment
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Message started by Anexanhume on Apr 20^th, 2006, 2:17pm

Title: Simple question about output assignment
Post by Anexanhume on Apr 20^th, 2006, 2:17pm

Hello all,

I am in a FPGA design class right now, and our VHDL/Verilog class is not listed as a prereq, but we have to code with it, so I'm stuck with a rather trivial problem.

It's a simple low pass filter, and Xilinx and Icarus alike tell me something along the lines of y not being a register. Perhaps you could tell me what is wrong, and maybe point out some things I did poorly in the code? Thank you very much.

Code:

module filter(clk,x,y);
input clk;
input [7:0] x;
reg [15:0] stage1;
reg [15:0] stage2;
reg [15:0] stage3;
wire carry2;
wire carry3;
wire [15:0] a1;
wire [15:0] b1;
wire [15:0] b2;
wire [15:0] sum2;
wire [15:0] sum3;

output [7:0] y;

initial
begin
stage1 = 16'b0;
stage2 = 16'b0;
stage3 = 16'b0;
end

always @ ( posedge clk )
begin
mult_const_b1( y, b1 );
add16( stage2, b1, 0, sum3, carry3 );

mult_const_b2( y, b2 );
add16( stage1, b2, 0, sum2, carry2 );

mult_const_a1( x, a1 );

assign stage1 = a1;
assign stage2 = sum2;
assign stage3 = sum3;

assign y[7:0] = sum3[15:8];
end

endmodule

Title: Re: Simple question about output assignment
Post by jbdavid on Apr 21^st, 2006, 1:34am

1 assignments are ALWAYS ON .. so don't put inside any block..

input A;
reg re3;
output y;
assign y = reg3; // whatever value reg3 has y will have FOR ALL TIME!!!

always @(posedge clk) begin
reg3 = A;
end

you didn't define mult_const_b1 .. I'm assuming its a function you declare?
I dont do FPGA's and try not to do digital w/o at least a V(Vdd) somewhere in the module!
<grin>
jbd

Title: Re: Simple question about output assignment
Post by Anexanhume on Apr 21^st, 2006, 6:08am

Ok, so when you say it will have that value for all time, it will also change with its value as well, hence the block that just changes the register?

Also, you were corect about the const functions. They are just functions which multiply the operand by a certain constant needed for my filter.

I redid the code, and got it to compile like this:

Code:

module filter(clk,x,y);
input clk;
input [7:0] x;
output [7:0] y;

reg [15:0] stage1;
reg [15:0] stage2;
reg [7:0] y;

wire carry2;
wire carry3;
wire [15:0] a1;
wire [15:0] b1;
wire [15:0] b2;
wire [15:0] sum2;
wire [15:0] sum3;

initial
begin
stage1 = 16'b0;
stage2 = 16'b0;
y = 16'b0;
end

always @ ( posedge clk )
begin
mult_const_b1( y, b1 );
add16( stage2, b1, 0, sum3, carry3 );

mult_const_b2( y, b2 );
add16( stage1, b2, 0, sum2, carry2 );

mult_const_a1( x, a1 );

assign stage1 = a1;
assign stage2 = sum2;
assign y = sum3[15:8];
end

endmodule

Title: Re: Simple question about output assignment
Post by jbdavid on Aug 3^rd, 2006, 5:53am

Yes. the output (a wire) is (in this block) assigned to TAKE its value from the register..
so you can set the value of a register in an always block,
but you do the assign before (or AFTER the end of the always block.. Never "inside"