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Design >> Analog Design >> Which analog design methodology you use?
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Message started by raul on Apr 28^th, 2006, 12:31pm

Title: Which analog design methodology you use?
Post by raul on Apr 28^th, 2006, 12:31pm

Hi,
I have found myself debating recently for a statistical process variation and mismatch based analog simulation methodology only. I thought most analog designers agree that the slow, fast, etc... models are good for digital designers and are only good for analog designers because they give some intuitive feedback to the designer about what process parameters affect the design and they are a quick way of checking if there is anything really wrong with your design. I generally will not run mixed corners like SF, FS because they are not real conditions that can happen given it's implied the oxide thicknesses of the devices will be different consistently between P and N in the same wafer.
In the end, statistical models have the final word and those are the numbers that should go into a spec compliance matrix. At least that's what i think. What do you think?

Title: Re: Which analog design methodology you use?
Post by Visjnoe on Apr 28^th, 2006, 3:03pm

Hello Raul,

I agree with your reasoning that corner conditions are extreme conditions and that a totally statistical design method would be more appropriate.
Often, corner verification leads to overdesign (more area/power)...

However, we too run zillions of corners: that's because a solid statistical design method requires you to obtain accurate processing data from the foundry. It's info there not always willing to share... Monte Carlo is only as good as the set-up an for the latter, you need foundry input...

Kind Regards

Peter

Title: Re: Which analog design methodology you use?
Post by ywguo on Apr 28^th, 2006, 11:34pm

Hi,

I agree with Peter that a totally statistical simulation is much more appropiate. Sometimes, the corner simulation doesn't disclose all faults of the circuit. I used to design a serdes. The silicon chip is of very poor bit error rate. We simulated the chip at SS corner, 125C, VDD-10% before tape-out. However, it had a timing error at SS corner, 100C, 3.3V when we simulated again.

Ideally monte carlo should be a good method, but it isn't often feasible because lack of foundy support and EDA support.

Best regards,
Yawei

Title: Re: Which analog design methodology you use?
Post by Paul on Apr 29^th, 2006, 5:41am

Hi everybody,

From an analog designer's point of view, I fully agree with the points of view expressed above. However, from a practical point of view, I'm not convinced MC simulation is a feasible alternative in all cases. Beyond the foundry support issue (which is a real problem), statistical simulation time may become too important if you want the statistics to be relevant. With corner simulations, you considerably reduce the amount of simulations you have to run and unsurprisingly you reduce the amount of information you get (nothing's for free...).

Yawei, your example doesn't hold to show the irrelevance of corner simulations, because the later corner sim revealed the issue. I must say that it is the designer's fault if he reduces the number of corners and omits some critical corners. I don't believe you would have seen the problem in MC simulations if you had omitted the 3.3V supply case.

Finally, as process engineers implement more and more compensation methods to tune the process for parameter variations, I wonder in how far the Gaussian assumption behind most MC models will hold for the sub 90nm nodes... Any info on this is welcome.

Interestingly some EDA providers start to deliver tools for yield optimization and design centering. I wonder how these will work with the current corner models we get ;-)

As design kits, as well as processes, are made for the mass (i.e. the digital designers), I don't think we can expect improved foundry support soon. We will probably have to stick with our "darned" corner simulations or trust our custom-made MC models.

Paul

Title: Re: Which analog design methodology you use?
Post by chase.ng on May 1^st, 2006, 12:31pm

Hi all,

I understand that nowaday some foundry actually provide a set variables that control the process variables in place of the standard FF, SF, etc corner. The tricky part is to figure what number to put into these variables to simulate a worse case condition. One way is actually running a monte carlo before hand and actually "calibrate" the variable to get the corner situation. But I found that hard to do so with large circuitry when they cannot even complete the MC simulation.

Regards,
Chase

Title: Re: Which analog design methodology you use?
Post by ywguo on May 4^th, 2006, 4:42am

Paul,

I agree with you. I just think it was easier to find the problem if I ran a Monte Carlo simulation at that time. Of cause I am not sure that Monte Carlo simulation must reveal all problems because nobody can simulate all corners, temperature, and supply voltages. :) Now we must rely on simulating in different corners. At least we get many info in much, much less time. I hope my comment above doesn't mislead newbies. Thanks, Paul.

Best regards,
Yawei

Title: Re: Which analog design methodology you use?
Post by Paul on May 4^th, 2006, 2:27pm

Yawei,

I guess we are all up to selecting the corner's which appear critical to us to keep the number of simulations within reasonable bounds and it may happen to any of us to miss a critical one...

Paul