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Design >> Analog Design >> Problem about the input common voltage of diff amp
https://designers-guide.org/forum/YaBB.pl?num=1146582526

Message started by pipeline on May 2^nd, 2006, 8:08am

Title: Problem about the input common voltage of diff amp
Post by pipeline on May 2^nd, 2006, 8:08am

I wonder how to determine the input common voltage of a simple 5 MOS transistors differential amplifier.For example, assume two NMOS's as the differential input pair with the PMOS's configured as active loads. I try DC sweep to find the skewest point of the transfer curve, but at that point, the CMRR is low too. Anybody help? Thanks!

Title: Re: Problem about the input common voltage of diff
Post by raul on May 2^nd, 2006, 12:29pm

You are going to have to decide what is the minimum CMRR or maximum voltage offset that you can tolerate and then sweep your input common mode range until you hit the limit of what you have decided that you can tolerate. The amp you describe will be limited on the upside by the Vt of the PMOS(drain of NMOS can't go more than one Vt below the NMOS gate) and on the low side by the VGS=Vgst+Vt of the NMOS+Vd,sat of the tail current source. If you want the best common mode input range from a classic topology you need a folded cascode structure.

Title: Re: Problem about the input common voltage of diff
Post by Paul on May 2^nd, 2006, 1:01pm

Hi,

as Raul already mentioned, the input CM range is delimited by the voltage levels, where one of the devices goes out of saturation. For lower input CM, it is the current source which will enter triode region, on the upper end it may either be the diff pair or the active loads. If you have a differential output, this will depend on your output CM setting.

Plotting the DC open-loop gain while sweeping the input CM should reveal both limits. Is this what you describe in your post? I don't exactly understand what operating point you select. In any case, in the middle of the obtained range, the gain should be maximum and the CMRR should be good. Don't go to close to either border in the typical case as this value somewhat varies with the transistor's threshold voltages.

Paul

Title: Re: Problem about the input common voltage of diff
Post by pipeline on May 3^rd, 2006, 12:14am

Thanks firstly!
I think I didn't describe the question clearly.
For a inverter amp, to get the largest gain, we should bias the input signal at the skewest point of the Vo-Vi transfer curve( as pointed in the attached bmp file ). However for a diff amp, if I try similarly, the CMRR is quite low, so am I on a wrong way? Generally, how to determine the input common voltage of a diff amp for further ac simulation?
Thanks.

Title: Re: Problem about the input common voltage of diff
Post by Paul on May 3^rd, 2006, 12:36am

Hi,

there are two issues in the way you run your simulation.
1) If you want to have a fully differential output, you must use common-mode feedback (CMFB) to regulate the pbias voltage. You cannot apply fixed current levels on either side of the diff pair, otherwise one of the current sources must go into triode region to compensate for the current mismatch.
2) The voltage gain is given by vout_diff/vin_diff, not by vout_p(n)/vi_cm as you plot it. In the presented graph, you obtain the input level for which the tail current becomes larger than the PMOS current. In order to plot the voltage gain, you must run an AC simulation with an AC differential input signal and plot vout_diff/vin_diff. Then you combine this AC simulation with a DC sweep of the CM voltage.

Does this answer your question?

Paul

Title: Re: Problem about the input common voltage of diff
Post by pipeline on May 3^rd, 2006, 1:13am

Thanks for Paul's detailed reply. I now get the point :)