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Design >> Analog Design >> low voltage buffer
https://designers-guide.org/forum/YaBB.pl?num=1146758007

Message started by grosser on May 4^th, 2006, 8:53am

Title: low voltage buffer
Post by grosser on May 4^th, 2006, 8:53am

hello everyone

i'm here the first time

could you recommend a buffer which will work fine with vdd=1.3V and threshold 0.6V or -0.75V.

simple source follower doesn't fit. i want it in LDO design, to move the second pole to higher frequencies.
nmos type source follower can fully turn on power device, but can't turn it off. the situation is inversely with pmos type source follower.

the buffer should be able to give large amounts of current to drive latge power device's capacity

regards

Title: Re: low voltage buffer
Post by raul on May 4^th, 2006, 11:31am

Like you said in your email; NMOS doesn't work because you can't turn-off the device under no load and standard Vt PMOS will not work at such low Vdd. You need to use a low-Vt PMOS follower or a Natural Vt NMOS follower based structure. Maybe you can lower the Vt of the PMOS power driver or PMOS buffer to save headroom at high load or lower the Vt of the NMOS follower if you don't have the two components previously mentioned.
I've got two patents on how to play this game, of course you can't use them unless you work at TI or a company that has cross-licensing with them, but you may get some inspiration:
1. US Patent 6,861,832
2. US Patent 6,646,495
Good luck.