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Simulators >> Circuit Simulators >> plotting verilog-a internals?
https://designers-guide.org/forum/YaBB.pl?num=1146975002

Message started by danmc on May 6^th, 2006, 9:10pm

Title: plotting verilog-a internals?
Post by danmc on May 6^th, 2006, 9:10pm

anyone know how (if possible) to plot an internal signal (electricaltype in my case) from a verilog-a module? The signal does not go to a pin. I'm using cadence. I took a look in the results browser in analog artist but didn't see any of the internal nets inside the veriloga model.

Thanks
-Dan

Title: Re: plotting verilog-a internals?
Post by sheldon on May 6^th, 2006, 9:26pm

Dan,

Doing this from memory, in the Outputs --> Save All window, select
save ahdl variables radio button. This should allow you to save and
plot the variables. However, you may need to access them from the
Results Browser.

Best Regards,

Sheldon

Title: Re: plotting verilog-a internals?
Post by danmc on May 7^th, 2006, 8:28pm

This almost works. I now see anything of type 'real' in the results browser, but still no 'electrical' ones. So, for now I just stuck in:

electrical foo;

real vfoo;

analog begin
vfoo = V(foo);

// other stuff

end

to make my signal show up as a real.

Thanks
-Dan

Title: Re: plotting verilog-a internals?
Post by sheldon on May 8^th, 2006, 6:18pm

Dan,

Oops in that case, try setting the option "select signals to output
(save)" to all in the Outputs --> Save All... window. Eletrical nodes
internal to a behavioral model are not public and are not saved by
default (as I remember).

Best Regards,

Sheldon

Title: Re: plotting verilog-a internals?
Post by ACWWong on May 9^th, 2006, 12:36am

Yes, default is "allpub", so changing it to "all" should give all internal nodes....