|
The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> The definition of worst case speed model https://designers-guide.org/forum/YaBB.pl?num=1147081133 Message started by reactgary on May 8th, 2006, 2:38am |
|
Title: The definition of worst case speed model Post by reactgary on May 8th, 2006, 2:38am Hi all, I am trying to simulate some circuit in cadence. The foundary (AMS) provided some worst case speed model. So, what is the definition of worst case speed model? Is it consider the effect of the worst case process parameter, is it included the effect of mismatch? Thank you Gary |
|
Title: Re: The definition of worst case speed model Post by vivkr on May 8th, 2006, 3:20am Hi Gary, Worst-case speed has nothing to do with mismatch. It typically implies high transistor VT, and low mobility. Regards Vivek |
|
Title: Re: The definition of worst case speed model Post by reactgary on May 8th, 2006, 11:30am Hi Vivek, Thank you for your answer Gary |
|
Title: Re: The definition of worst case speed model Post by mikki33 on May 17th, 2006, 3:15am vivkr wrote on May 8th, 2006, 3:20am:
And high temperature as well |
|
Title: Re: The definition of worst case speed model Post by raf on Jun 1st, 2006, 2:52pm The temperature you have to set yourself. Probably to 120. |
|
Title: Re: The definition of worst case speed model Post by hamed on Jun 2nd, 2006, 2:14am * Referring to last comment about temperature: The Vt of CMOS transistor decreases as temparature increases, So in worst case for speed, one has to combine lowest temperature with low speed corner (high Vt). Hamed |
|
Title: Re: The definition of worst case speed model Post by always@smart on Jun 2nd, 2006, 5:14am hamed wrote on Jun 2nd, 2006, 2:14am:
Hamed, I agree with you. Worst case supposed to be high Vth, Low mobility and at low temperature (-40). In this case, circuit usually produce lowest current, therefore lowest speed. Regards, Smart |
|
Title: Re: The definition of worst case speed model Post by mikki33 on Jun 3rd, 2006, 4:09am I can't agree with that. The degradation of mobility with growing temperature is going much faster then reduction of Vt. So, use SS process corner, the lowerst supply voltage and the highest possible junction temperature Take ring oscillator of 7 invertors and check the frequency as a function of temperature in TRAN simulation and won't be surprized. |
|
Title: Re: The definition of worst case speed model Post by hamed on Jun 5th, 2006, 4:30am Hi mikki33, Please check out the following: "Analysis and Design of Analog Integrated Circuits" Gray, Hursr, Lewis, Meyer - (Foth Edition) page 47,48 Regarding your special example, there could be other reasons for. Just to give you an idea, consider another similar example: with cascading few inverters you decrease the delay and increase the speed!!! Hamed |
|
Title: Re: The definition of worst case speed model Post by mikki33 on Jun 7th, 2006, 4:43am Ok. I am designing CMOS analog during last 11 years, and according to my experience, high temperature increases delays. I just did the simulation, I suggested in my previous post. Ring oscillator, 7 inverters, 0.13 u process from very respectable FAB, model: BSIM3v3, supply 1.2V and 3 different TEMP 25, 70 and 125. No parasitics, ideal supply. The slowest corresponds to 125 deg C. |
|
Title: Re: The definition of worst case speed model Post by ACWWong on Jun 7th, 2006, 5:21am sorry to butt-into this conversation... i agree with mikki... slow speed for CMOS circuits is usually at high temperature... inspite of vth reduction... |
|
Title: Re: The definition of worst case speed model Post by fran2k5 on Jun 7th, 2006, 8:15am Hello everybody, I agree with mikki33 as well. Please note that the degradation of mobility depends on the movement of the crystalline lattice. Regards, fran2k5 |
|
Title: Re: The definition of worst case speed model Post by hamed on Jun 14th, 2006, 6:23am Hi all, I think one has to be careful when defining "worst case" for analog or digital designs. While in analog circuits, Vth is the most meaningful parameter which "Slow Cornet" is defined based on that, in digital circuits gds and capacitors determine performance of the circuit in terms of the speed, and Vth is almost meaningless. That's why the "slow corner" gets worse if temperature decreases (Vth increases). In addition there are some cases in which the interaction of devices behaviour changes the whole performance in a direction that may looks strange. Hamed |
|
Title: Re: The definition of worst case speed model Post by vivkr on Jun 19th, 2006, 6:00am hamed wrote on Jun 14th, 2006, 6:23am:
Hi Hamed, I would be wary of making a statement like that. The most important parameter in analog design is arguably the transconductance (Gm) of the device. In fact, even in digital circuits, which are analog in reality, the same holds equally true. And Gm depends first on mobility of the device (Kn'= un*Cox). Vth is a composite of several quantities, and ideally ought not to influence the speed. However, a larger Vth implies a higher overdrive to achieve the same Gm in the device. So both un and Vth are instrumental here. The fundamental speed of the device is proportional to un/L, and hence shorter channels offer higher speed due to reduced transit time. Please keep in mind the following: 1. Vth variation across process is strongly dependent on doping and oxide contamination as far as I know (Vth here implies threshold voltage). 2. If wafer A and B have the same un (mobility) & Cox & L but differ only in Vth, then the wafer with the larger Vth is the slower one. However, Vth alone cannot provide speed information. 3. Given a wafer, the speed will typically reduce with temperature despite the reduction in Vth at higher temperature. This is due to the fact that the mobility reduction due to higher temperatures has a stronger impact on speed than Vth reduction. Hence, the worst-speed situation is for worst-speed process (highest Vth, lowest Kn') and highest temperature with lowest supply. 4. Thus, the worst-speed corner assumes lowest un, highest Vth, and also longest L (in good process models). 5. Perhaps there are some special circuits which behave a bit differently, but in general the device transit time should increase as the temperature goes up, and this is the fundamental criteria for testing the speed of a device. Regards Vivek |
|
Title: Re: The definition of worst case speed model Post by hamed on Jun 22nd, 2006, 1:42am Hi Vivek, Thanks for your comprehensive and useful note. Regards Hamed |
|
Title: Re: The definition of worst case speed model Post by Croaker on Jun 22nd, 2006, 4:28am ACWWong wrote on Jun 7th, 2006, 5:21am:
My understanding is that mobility is increasing (as temp goes up) at low temperatures because the ions will have less effect on a hotter carrier. Then mobility decreases because the lattice vibrates and there are collisions. So the curve of mobility vs. temp is an inverted 'V'. The Vth change is -0.6 mV/K but mobility goes down with T^(-1.5), so yes, mobility is going to really affect your circuit speed more. Plus Ids is a linear function of Vgs-Vth with short-channel devices, so the temp has less of an effect on current via Vth than for square-law devices. Cheers, Marc P.S. I am using the handle 'Croaker' now. It comes from the 'Black Company' books. |
|
Title: Re: The definition of worst case speed model Post by akhtaralam on Jun 22nd, 2006, 5:42am Thanks Vivek, I'm fully in sync with your explanation. Thanks, -Akhtar |
|
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |