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Design >> Mixed-Signal Design >> sigma delta noise analysis problem
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Message started by chungmnig on May 16^th, 2006, 5:04am

Title: sigma delta noise analysis problem
Post by chungmnig on May 16^th, 2006, 5:04am

Hi~~
I had seen "Device noise simulation of delta-sigma modulators" written by Ken Kundert.
But my simulation time is so long because i use chopper stabilization inside , it has many clocks.
So i think can i just noly simulate OPAs noise (because noise mainly introduced by OTA ,flicker,thermal)
then use input referred noise in OPA's input by verilog-A .
Is this simulation accuracy?

Title: Re: sigma delta noise analysis problem
Post by vivkr on May 16^th, 2006, 5:19am

Hi,

I don't think it is reasonable to attempt a full transistor level noise simulation of a delta-sigma modulator for
two reasons:

1. It will take far too long.
2. You cannot do Pnoise and PSS analysis as the modulator operation is inherently chaotic.

The best bet would be to first budget the noise for different stages. Typically, the first stage should dominate
the overall electrical noise. Then, you can estimate the maximum permissible thermal noise floor in your design
based on this, and taking into account the aliasing of wideband noise (number of settling timeconstants), and the effect
of the chopping scheme if it adds any extra noise. With the discrete-time transfer function of the first integrator, you
can estimate its gain at the edge of passband and get a number for the maximum allowable noise from the rest of the circuit.

I would suggest you do Pnoise simulation (if you wish) only on the first stage integrator as this typically
is the dominant noise source of all electrical noise sources. If you are not sure about the relative contributions of
the different stages, you can either estimate this by hand calculation, or just run a PSS on the modulator without
the quantizer and with zero input and reference DC levels. However, I would suggest the hand calculation approach.

Regards
Vivek