The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> LDO Stability check ...
https://designers-guide.org/forum/YaBB.pl?num=1148005890

Message started by always@smart on May 18^th, 2006, 7:31pm

Title: LDO Stability check ...
Post by always@smart on May 18^th, 2006, 7:31pm

Dear All,

This is my FIRST post in this forum, hope someone can help me out ...

I recently design an LDO and it is used to drive some cascaded large inverter. What should I put as the load for the ac analysis?
I have read some papers, they just put a RL (which equivalent to the sinking current at the load). I did so to put RL (and a current source) for 0A to 8mA, and i got good PM at all corner. Which is better, a current source or RL?

However when I plug the Inverters as a load, the LG and PM vary alot at all corner. For example the LG may drop 10db or may go upto 70dB. The PM may drop to negative or some case it may goes beyond 180 degree (which is weird).

I found out that the impedance of the inverter (i unpluged it from LDO, give VDD , ac=1), vary from few hundred ohms to few hundred mohms, this might cause the LG (gain of the PMOS) vary. The reason behind this is because the inverters is fed from a Limiting Amplifier which Output Commod Mode is 1.2V, and it may vary across all corner, this cause the DC point of the inverters change and eventually , at different corner, MOS of the inverter operate at different region.

For the transient analysis, what kind of setup should I do for my circuit? Should i give a step response at the VDD_Supply Voltage step 0-3.3v (with inverters) or current step 0-8mA (without inverters) at the VDD ?

Thanks in advance

Regards,
Smart

Title: Re: LDO Stability check ...
Post by raul on May 18^th, 2006, 11:26pm

Without seeing the architecture you are using, it is somewhat hard for me to imagine why you are seeing some of the things you describe. You mention PMOS, so i assume you are using Miller compensation in which case no load & low ESR should be your worst case stability condition. It would be helpful if you post what test condition causes what PM or LG change, etc...
A fool proof way of checking stability is the transient load step test. Check how much is your maximum load current and use a pwl current source with a 1 ns rise and fall time and let it run long enough for the output voltage to settle after the overshoots subside. By looking at how much ringing you have you should get a good idea of how stable your loop is. Make sure you set your transient analysis tolerance to conservative.
AC simulations should correlate if you break the loop correctly and mimic all the necessary capacitances at the break point. If AC doens't match transient i'd believe transient analysis.

Title: Re: LDO Stability check ...
Post by always@smart on May 19^th, 2006, 2:24am

Dear Raul,

Sorry, I should have given the diagram earlier. Please refer to the attachment...

You would notice that the 1st stage inverters input is fed from Limiting Amplifier (LA), which has common mode around 1.15 ~ 1.25 accross all corner. The LA supply is from different voltage regulator. The inverter supply from LDO, this LDO does not have external capacitor, internally there is a 100pF cap, and the error amplifier is a 2 stage OTA. The maximum switching current flow through VDD24 is 8mA.

I have done 3 type of stability check for the LDO:
1. I unplug the inverters, and putting a estimated CL ( for the inverters capacitance) and RL= 300 ~ 2.4M ohms (equavalent to current sink from 1uA-8mA) at the output of the LDO. I manage to get good PM (around 70 degree) with no much LG variation (around 60 to 70dB)at all corner(provided all MOS in saturation). No matter i break the loop at PMOS's gate or the resistor node, the result show almost the same.

2. I unplug the inverters, and putting the CL and a current source (0-8mA) at output of the LOD. This setup also giving me good PM and no t much LG variation at all corner. I have a question here. comparing the setup 1 which using a RL and the setup 2 using current source, which give more accurate result. In this two setup i do not see it take the load impedance into account , or does it?

3. I plug the inverters as the loading of the inverter, and the LA operate at Common Mode=1.2v. However this time the PM and LG vary lot, PM can vary from negative, and to more than 180 degree (kinda weird, right?). The LG can vary from 5dB to 70dB. Here I do some more analysis, I measure the inverters impedance (by giving a Vdc=2.4, ac=1), the impedance vary from 100 mille ohms to 400ohms, due to the DC point of the inverters from LA is changed across all corner and causing the inverter operate at different region. Should I trust this result?

I have done the transient analysis (without inverter) as mention by raul, putting a ipwl and sweep current from 0-8mA within 1ns. The VDD24 show very stable , without any overshoot and ringing.

I have a question here, should I put the inverter back, and sweep the VDD33 and provide the Common Mode=1.2V to the LA input (similar to the 3rd setup in AC analysis)?

Any other inputs are all welcome

Thanks in advance

Regards,
Smart

Title: Re: LDO Stability check ...
Post by raul on May 19^th, 2006, 5:25pm

Hi Smart,
I would suggest a number of things:
1. Why do you need a 2-stage OTA? That leaves you with three gain stages counting the power PMOS, this is going to be difficult to compensate/stabilize and your open loop gain is pretty low for such a large amount of gain stages anyway. You could use a cascoded gain stage folded cascode and get as much gain as you get with the two-stage OTA. Then with Miller compensation you can easily split the poles of your two gain stage system. Since you don't have a load capacitor ESR either, you don't have a zero to try to help you compensating this system. Here you have no choice than to keep it simple to make your life easy.
I think that your stability problems are probably due to the output node's impedance varying widely since the impedance of this node (when it is high) will give you a pole that will move towards lower frequency and it will be getting close to the other pole that is not being split by Miller comp in your 2-stage OTA.

Title: Re: LDO Stability check ...
Post by always@smart on May 19^th, 2006, 8:59pm

Raul wrote on May 19^th, 2006, 5:25pm:

Dear Raul,

Thanks for your input.

Firstly, I would try your suggestion by changing the 2-stage OTA to folded-coscode OPA.

However, I believe it might be able to solve the PM problem, but the LG problem in the setup 3 i mentioned in last post will still exist, since i notice that, If I plug the inverter for AC analysis, the gain of the Power MOS can vary from -10dB to -40dB (depending on the inverter's Impedance )and cause the LG drop to 5dB to 50dB.

What would you say regarding this phenomenon?

2. For the AC analysis, putting current source or a RL, which is better setup?

3. What supposed to be appropriate LG for feedback factor is 1/2?

Will get back to you once i have done the new LDO with folded-cascoded OPA.

Regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 21^st, 2006, 5:36am

First, since the LDO you are using is for the application of digital power supply, I think the setup with RL is more accurate. From my point of view, with the ideal current source , it is so strong that make the setup of DC operation point easier.

Basiclly, I agree with the Raul that in order to make your life easy, it is better to use cascode or folded cascode structure instead of 2-stage OTA since you have to be very careful for the compensation of multistage amplifier.

For your circuit diagram, I will treat your 2-stage OTA just as an OTA block regardless of the detailed structure inside. Then, the diagram you shown is reduced to a two poles system. The output of OTA comtributes one pole, and the other is located in the output VREG2.4. Two-poles system is inherently not stable, this is why you add miller compensation capacitor to split the two poles. A left-hand plane zero is contributed by the compensation resistor and capacitor, this can help in keeping the phase margin.

For the tradiotional LDO design, large output capacitor is needed in order to stabilize the system, by which I mean that the dominant pole is situated at the output regardless of the load current. However, this is not the case in your circuit if not mistake. The 100p F is too small to make the output node dominant in all the range from 1uA to 8mA, this is not good for stability. What is more, the miller compensation cap is added to just make the output node of OTA more dominant. So, I assume that the dominant pole is at the output of OTA.

You mentioned that both setup 1 and setup 2 give very good PM. I think this is not surprise. since the dominant pole is situated in very low frequency(if you use the 2-stage OTA, then the output impedance of OTA would be very large, plus the big miller compensation capacitor, this pole is in very low frequency indeed). Hence, the consequence is to make these two poles well seperated and what's more, you have one left-hand plane zero to keep the phase. This is why you did not see any change from the frequency response when you tune the RL or IL in a large range. If you reduce the value of miller compensation cap or increase the decoupling cap, you will see the difference.

For the setup 3 where you plug the inverters in, I am fine with the way you find the equivalent impedance. If not mistake, you swept the DC voltage of the input which comes from the LA(this equilatent to RL), and saw the frequency response. The weird thing you find is most probably due to that under certain condition, the LDO is out ot regulation , or in other word, the current vaule is beyond the current capability of the PMOS pass transistor. Suppose you have 100 milli ohm, then current being sink should be 2.4/(100*10-3)=24 Amp. This is huge !!! , indeed. Of cause, if you take 400 ohm, the sink current 2.4/400=6 mA, then this value is within the 8 mA specification of you LDO design.

However, the problem with this setup 3 is that during switching or in transient simulation, the impedance change of the inverter is rather difficult and more than the way you use in setup 3 since it is a switch(characteristic of digital circuits). Pluging the inverter to find the frequency response ,that is nothing help. This accounts for why you did not find any problem during the transient simulation while there is weird things with setup 3 frequency simulation, by which I mean setup 3 could not represent the real situation.

what I suggest:

1. RL and CL as load,
2. make sure even in the worst case, you still have decent phase margin, just as Raul mentioned before. In your case, lowest current condition.
3. The most important thing: do the transielant simulation with your real digital circuit. In your case, adding the cascaded inverters.

if these test all pass your sepcification, then it is ok anyhow.

Hope this can help ! I would really like to discuss with you guys on this.

taofeng

Title: Re: LDO Stability check ...
Post by always@smart on May 21^st, 2006, 10:59am

Dear taofeng and Raul,

Thank u very much for your reply.

First of all, I have already implemented the new LDO with single stage folded cascode OTA (Gain=60dB). The Load capasitor maintains same 100pf with additional CL (0.1pf to 10pf) for inverter, Pad and the Probe cap.I just use a 10pF compensate capacitor that connector btw the gate and drain of the Pass Transistor (PMOS) or maybe can you refer me a better compensation?

Setup 1. Ok, I agree with taofeng, which the current source setup might be mainly for DC point checking to ensure the PMOS is still maintaing in saturation with the MAX current sink. I have a question here, do i have to worry that with minimum current (1uA) sink the PMOS goes to weak-inverton region (Vgs slightly smaller than Vth)?

Setup 2. With the RL and CL, I managed to get good PM (at least 60) at all corner even at 1uA current sink.

Setup 3. This time although I plug the LDO with the Inverter, the PM show almost the same result as setup 2, apart from LG still has quite big variation.

I have some worry here, with only a CC compensation, I can see there is a zero introduce in btw dominant pole and the 2nd pole, can you explain this?

I will show you guys the bode plot if it is necessary .

regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 21^st, 2006, 12:43pm

For the simple 2-stage LDO design , I think the simple miller compensation is good enough.

You do not have to worry about the weak-inversion effect, since it is normal that your PMOS pass transistor experiences the saturation, linear and sub-threshold regions with so wide variation in the load current. However, the advantage of making the PMOS pass transistor always in saturation is that it could ensure a high output impedance of PMOS, which is good for the PSRR, especially in high frequency.

What do you mean the CC compensation ? if you mean only CC compensation (without compensation resistor RC), then most probably the zero in between the dominant pole and second pole is caused by the parasitic pole in side the folded cascode OTA. However, if you mean CC compensation with the compensation resistor RC, then the zero is caused by the CC and RC, which is very apparent.

I do not know if I make it clear for you ?

Could you please attach some simulation results ?

best regards,

taofeng

Title: Re: LDO Stability check ...
Post by always@smart on May 22^nd, 2006, 4:46am

Dear taofeng and all,

Thanks for your input.

Referring to the attachment.

As I have mentioned earlier, this LDO is designed with folded cascode, 100pF internal capacitor with a 10pF compensation capacitor accross gate and drain of pass transistor (without RC). The Bode Plot as noted with "A" is plot for RL=300ohms and "B" is RL =2.4Mohms. Both PM giving good result (>80 degree). Both "A" and "B" have a Zero introduce in between 2 dominant poles (although it's not clear in "B"). Bear in mind this running with setup 2 as I mentioned early.

Now when i do setup 3 (plug invertes for the load, CM of LA=1.2V) and I give a step response to VDD33, the result looks good at temp -40 and 27 (inverter current sink is about 1mA). However some kind of oscillation showing when temp =125 (inverter current sink is about 3mA). Can anyone explain this , how can I solve it?

Maybe it's the compensation problem, please advice me a better method if you have ...

Hope someone can help.

Thanks in advance

Regards,
Smart

Title: Re: LDO Stability check ...
Post by always@smart on May 22^nd, 2006, 4:54am

Dear all,

Sorry i just have no idea how to attach 2 files in a post.

Here is the transient result.

regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 22^nd, 2006, 7:48am

It is strange indeed.

If the folded-cascode OTA is designed approriately, by which I mean all the internal poles and zeros are (well) beyond the unit-gain frequency, then you only have two donimant poles left: one is at the output of OTA, and the other is at the VREG2.4. Since you do not have RC , then there should be no left-hand plane zero to keep the phase margin. However, from your simulation plot, it seems there is a zero(maybe unintentional), so I think it is probably due to the internal node inside the OTA. Check the OTA circuit, or could you please plot the gain and phase @ the output of OTA ?

Second, you should really ask yourself that: which pole should be the dominant one ? I am wondering you have swappable dominant pole here when you change the load current. From my point of view, this is not recommended in terms of stability. Suppose, when in 2.4M ohm condition, the pole at VREG2.4 is 1/(2*pi*2.4*1e6*100*1e-12)= 663 Hz. How is the output of the OTA, let's assume that the output impedance of OTA is 10M ohm and there is no miller effect(since the gain is approximate zero in this 1uA load condition), so 1/(2*pi*10*1e6*10*1e-12)=1592 Hz. these two poles are of cause not well seperated.

Finally, I am not fully understand the simulation setup for the step in the VDD3.3. is this kind of Line regulation ? I don't think so. How large the value and step of you stimulus ?

hope this helps !

regards,

Junfeng

Title: Re: LDO Stability check ...
Post by taofeng on May 22^nd, 2006, 7:54am

could you also please tell how and where you cut the loop ?

Title: Re: LDO Stability check ...
Post by always@smart on May 22^nd, 2006, 10:50am

Dear Jun Feng,

Thanks for your reply.

Let me answer your question that i can answer at this moment (I'm at home now=). )

could you please plot the gain and phase @ the output of OTA ?

You meant to check 1. open loop gain or 2. the loop gain, since i have already broken node between output of the OTA and the gate of the pass transistor to get the LG and PM, please clarify this so i will show you the result if you meant the 1st case.

I am wondering you have swappable dominant pole here when you change the load current

Ok, I suppect this situation happen in the circuit too. Before i am putting the Compesation Capacitor=10pF(without RC), the two dominant pole are about 10~100 decade seperated away. I will get back to you regarding the exact result before and after compensation which node playing more dominant. Any other details you need?

Finally, I am not fully understand the simulation setup for the step in the VDD3.3. is this kind of Line regulation ? I don't think so. How large the value and step of you stimulus ?

In fact there are 2 possible input point (after the LDO is connected with the inverters) for checking the step response in my circuit 1st. the VDD3.3 and 2nd. the input of the LA (which is differential signal). I have chosen VDD33 for step response (0v at 0s and 3.3v at 10ns ) to simulate when the LDO is poweredp and the LA i have given it's Common mode which is 1.2v (this might not be correct one).The result was shown in my last post. You are welcome to comment this setup. =)

could you also please tell how and where you cut the loop ?

Simply cut between OTA's output and the Pass transistor's gate. I am using C@dence Spectre, so at the broken points, I inserted a "Iprobe" (it will take care of the DC poin just like Middlebrook), and run the stability analysis in Spectre. I have also tried breaking node btw resistive feedback and Vp of the OTA, it shows almost same result.

Anyway, I will get back to you later. In the meanwhile, If you have any further comment please advice me...

Thanks in advance.

Regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 22^nd, 2006, 12:13pm

Of cause, I mean open loop gain. In detail, I want to know the open loop gain/phase of the OTA (the first stage) and the open loop gain/phase @ VREG2.4 (which is the total gain of the 2-stage ), you can plot in the same graph.

Basically, I agree with you that no matter where you cut the loop, the simulation results would be almost the same. However, the traditional way is to break at the node beween resistive feedback and Vp of the OTA. By doing this, you can check the gain/phase of the first stage(OTA).

From your simulation above, I see that the overal gain is around 60dB if not mistake. However, you mentioned before also that the OTA itself gives 60dB, which means that your Pass transistor does not have any gain or the gain is so very low ? it is weird actually.

I would suggest the following things:

1. pick-up the folded-cascode OTA only, and do the pole -zero(stability) analysis, by which I mean the open loop analysis.
2. sweep the RL in a decent range, let's say 1k to 100k, and plot the gain/phase.
3. increase the ramping up time from 10ns to let's say, 1us, just to see if there is any difference. Because 10ns is too fast to activate the loop(10ns means 100MHz bandwidth, it is impossible for your case with the miller compensation. From your simulation above, the bandwidth is from 2MHz to 25MHz, so take 1us as an example ).

hope this helps !

best regards,

Junfeng

Title: Re: LDO Stability check ...
Post by uncle_ezra on May 23^rd, 2006, 4:25am

I have designed a similar circuit and from the diagram your circuit have 2 dominant poles. The compensation you are using won't help at all. How large is the pass transistor?

I would compensate either by adding ESR (if permitted) in the output so a zero is created or use NMOS or native NMOS (if available) as your pass transistor.

Title: Re: LDO Stability check ...
Post by always@smart on May 23^rd, 2006, 6:06am

Dear Jun Feng and uncle_ezra,

Thanks for your reply.

Let me answer the question before I ask something else.

From your simulation above, I see that the overall gain is around 60dB if not mistake. However, you mentioned before also that the OTA itself gives 60dB, which means that your Pass transistor does not have any gain or the gain is so very low ? it is weird actually.

In deed the OTA's gain is around 60dB, the total LG is around 60-80dB which is with feedback factor about 0.5 (-6dB).

you should really ask yourself that: which pole should be the dominant one ?

Before compensated, the dominant pole located at output of OTA, which is around 2kHz and the second pole at output which is around 500khz, PM is around 10 degree.

After putting CC=10pF, the dominant pole still at output of the OTA.

I would compensate either by adding ESR (if permitted) in the output so a zero is created or use NMOS or native NMOS (if available) as your pass transistor

I'm not allowed to use external cap, only internal 100pF is allowed. Using NMOS is possible, but can the OTA work with output range 2.4~ 3.0(with NMOS's Vth=0.6V and VDD=2.4V) at all corner (even VDD_Supply=3.0v)? Please share your idea.

Now is my turn to explain something i have discovered.

I have realized that that the Trans result i have shown early is due to a current surge from the inverter, this is due to Vcm of LA =1.2v, at some case, it caused the inverter change the oparating region, when VDD3.3 ramp up hence VDD2.4 also, this (current surge) cause the LDO operate unusually (the gate and drain of the PMOS raise at same time).

To solve this problem, I have put additional Rmin resitor at the VDD24D, to make sure the minimum amount of current sink from the Pass Transistor, now, the "oscillation" thing has gone, the trade of is additional static current. I have attach a graph, which is I give a current pulse (10us rise/fall time) at the VDD24D without connecting inverter (I call it setup 4). You can see when the although the VDD24 has already stable, when there is a large current rise/fall fast, the VDD24 will fall/rise, which is out of the regulation. Maybe this is one of reason, why usually LDO put a large capacitor externally to prevent spike, is it? Maybe someone can explain this?

Hope someone can help, Thank you in advance

regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 23^rd, 2006, 6:43am

wheather or not out of regulation depends on you application, since this LDO is for digital power supply, then let's say within plus and minus 10% of 2.4V is tolerant. How is yours ?

Yes, for the traditioanl LDO design, large cap is needed to reduce the undershoot and overshoot during current ramp-on and off.

Do you mean you add additional resistor to sink some current in the start-up simulation ? pls remember add a small resistor, means that the output resistance is reduced (since resistors are in parallel), which means that the output pole is shifted to high frequency. All means that your LDO is not stable enough, you can achieve stability by increase the value of compensation cap instead of increasing the quiescent current.

how is the problem with open loop simulation? I mean the strange zero ...

best,

junfeng

Title: Re: LDO Stability check ...
Post by always@smart on May 23^rd, 2006, 7:45am

Dear Jun Feng,

Thanks for quick response.

wheather or not out of regulation depends on you application, since this LDO is for digital power supply, then let's say within plus and minus 10% of 2.4V is tolerant. How is yours ?

As you can see from my previous transient simulation for setup3 (LDO with inverters, ramping VDD33), the VDD24 latch-up to about 2.8v, which is more than 10% of 2.4V.

Yes, for the traditioanl LDO design, large cap is needed to reduce the undershoot and overshoot during current ramp-on and off.

Do you mean spike?

Do you mean you add additional resistor to sink some current in the start-up simulation ?

This additional Rmin resistor is to maintain a minimum amount of current sink from the PMOS, hence it will eliminate the large ouput impendance for low current load. This can prevent the ouput pole shifted to become dominant pole when low current load case. It's so far work for me, I will do more analyisis on this and tell u the details (this is one of the method written in a book).

you can achieve stability by increase the value of compensation cap instead of increasing the quiescent current.

I have tried a increase the CC to even 50pF, although AC analysis show good result (without inveters) but still when comes to setup3 simulation, the "oscillation " still exist. At least so far adding the Rmin I see good result.

how is the problem with open loop simulation? I mean the strange zero ...

Sorry i haven't done this simulation. Can you please explain what is the setup for the open loop simulation?

How about your LDO design, any issue you face? Please share with me, maybe some hidden problems that i have not discovered

Best regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 23^rd, 2006, 8:33am

As you can see from my previous transient simulation for setup3 (LDO with inverters, ramping VDD33), the VDD24 latch-up to about 2.8v, which is more than 10% of 2.4V.

this is kind of trade-off. Basically, from my point of view, this can be solved by:

1. increasing the Cdeoupling(acting as energy reservior) . Since the 100pF is fixed, you have no choice.
2. increasing the bandwidth of the loop(make it faster). you have to increase the bias current (power increases)or decrease the CC, but there are stability risk associated with it.
3. increasing the size of pass transistor to see if it helps.
4. to reduce the time of current ramp-on and ramp-off. But , it depends on your internal digital circuit. make some approximation about how fast you current ramp on in the worst case.

Do you mean spike?

yes , I mean the spikes which is cased by the current ramp-on and ramp-off.

This additional Rmin resistor is to maintain a minimum amount of current sink from the PMOS, hence it will eliminate the large ouput impendance for low current load. This can prevent the ouput pole shifted to become dominant pole when low current load case. It's so far work for me, I will do more analyisis on this and tell u the details (this is one of the method written in a book).

I kind of understand the simulation of setup 3. It can be understood by the PSRR,I think. The Rmin you add is in parallel with RL, gives (Rmin//RL), which then is in series with the ouput impedance of pass transistor Ron, they act as a voltage divider before the loop is activated. Hence the smaller the Rmin you add , the smaller the volatage on VREG2.4 node. Also increasing the time of power up to micro seconds, then see if there is different. 10ns is too fast.

I have tried a increase the CC to even 50pF, although AC analysis show good result (without inveters) but still when comes to setup3 simulation, the "oscillation " still exist. At least so far adding the Rmin I see good result.

increasing the CC has nothing to do with your PSRR(setup 3) before the loop is activate, this only makes loop slower, and hence cause the oscillation.

Sorry i haven't done this simulation. Can you please explain what is the setup for the open loop simulation?

it is not that difficult , I think , many book has such kind of configuration.

How about your LDO design, any issue you face? Please share with me, maybe some hidden problems that i have not discovered

you can see the post I have put on, we have almost the same structure , but different problem. any idea ??

regards,

Junfeng

Title: Re: LDO Stability check ...
Post by always@smart on May 23^rd, 2006, 10:22am

Dear Jun Feng,

Let me clarify the setup of the open loop before i do it later (next morning).

setup 5.

1. break the feedback point. VP and resistive feedback.
2. give the Vp=Vn=1.2v (default dc point)
3. give Vp, ac=1
4. do ac analysis
5.check the open loop gain/phase of the OTA (the first stage) and the open loop gain/phase @ VREG2.4 (which is the total gain of the 2-stage )

is this what you wanna see?

regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 23^rd, 2006, 10:51am

yes , exactly right.

good luck,

Junfeng

Title: Re: LDO Stability check ...
Post by uncle_ezra on May 23^rd, 2006, 5:43pm

I dont quite understand how you are breaking the loop. Usually you use a large inductor and capacitor together with an AC source to break the loop. The inductor is to provide dc bias while blocking the AC signal and the capacitor is used to couple the AC signal and block DC.

One other method is to use the iprobe in Cadence and run stability analysis. Either way works

Title: Re: LDO Stability check ...
Post by uncle_ezra on May 23^rd, 2006, 6:03pm

A 2 stage amplifier using Miller compensation results in the following 2 poles:

p1=1/(gm*R1*R2*Cc)
p2=gm/(C1+C2)

Usually p1 would be dominant pole and p2 would be pushed beyong UGF. However in this case C1 and C2 are huge which would result in 2 poles system and hence unstable.

Does anyone agree with me or am I wrong?

Thanks

Title: Re: LDO Stability check ...
Post by always@smart on May 23^rd, 2006, 6:49pm

Usually you use a large inductor and capacitor together with an AC source to break the loop. The inductor is to provide dc bias while blocking the AC signal and the capacitor is used to couple the AC signal and block DC.

Yes, this method is so-called Middlebrook.

One other method is to use the iprobe in Cadence and run stability analysis. Either way works

I prefer this method (and I'm using it for stability check), someone has mention "iprobe" provide slightly better accuracy.

Regards,
Smart

Title: Re: LDO Stability check ...
Post by always@smart on May 24^th, 2006, 3:32am

Dear Jun Feng,

I have already simulate the Open loop gain and PM.

For the OTA A=60dB, BW=5.4k Ro=2.4Mohms, PM=80

For the 2-stage open loop, R0=28ohms, A=15dB (-44dB contribute by PMOS, since it's in linear gmRo=210u * 28ohms), PM=85.

What can you see from this info?

Regards,
Smart

Title: Re: LDO Stability check ...
Post by taofeng on May 24^th, 2006, 4:08am

would it be nice to post the simulation ?

plot the gain/phase @ output of OTA and @ VREG2.4

annotate what is the load condition.

good luck

Title: Re: LDO Stability check ...
Post by taofeng on May 24^th, 2006, 4:34am

For the OTA A=60dB, BW=5.4k Ro=2.4Mohms, PM=80

something you need clarify:

BW=5.4k is the first dominant pole ?
Ro=2.4Mohms is the output impedance of OTA or your RLoad ?

For the 2-stage open loop, R0=28ohms, A=15dB (-44dB contribute by PMOS, since it's in linear gmRo=210u * 28ohms), PM=85.

I can not fully get it. how come the total gain of the two stages becomes only 15dB ? it is too small, at least larger than 40dB. It is not good design at least in the load condition, what is your load in this case ? try to tune some parameters, I think the size of PMOS pass transistor is too small if not mistake ?

good luck

junfeng

Title: Re: LDO Stability check ...
Post by always@smart on May 24^th, 2006, 6:54am

Dear Jun Feng,

BW=5.4k is the first dominant pole ?
Ro=2.4Mohms is the output impedance of OTA or your RLoad ?

It's the BW and R0 of the OTA, which is the frequency response at the output node folded-cascode.

how come the total gain of the two stages becomes only 15dB ? it is too small, at least larger than 40dB. It is not good design at least in the load condition, what is your load in this case ? try to tune some parameters, I think the size of PMOS pass transistor is too small if not mistake ?

THe Load is RL which connecting inverters. The reason behind this is , I open the loop an give vn=vp=1.2v, and vp ac=1, the loop now is completely open, there is no feedback which is adjust the dc point. the current flow tru the PMOS is around 130uA and VDD24 =135uA * 24k=3.28v and the PMOS has gone to linear region, which then provides small gm. (It won't happen like this in actually circuit with feedback, the PMOS will be always in saturation).

Do you have to make sure all the MOS still in saturation even in open loop circuit?

Regards,
Smart

Title: Re: LDO Stability check ...
Post by always@smart on May 24^th, 2006, 6:57am

would it be nice to post the simulation ?

plot the gain/phase @ output of OTA and @ VREG2.4

annotate what is the load condition.

Sorry but I have to post the graph that you wanted to see tomorrow with the circuit setup if nessasary.

Regards
Smart

Title: Re: LDO Stability check ...
Post by uncle_ezra on May 24^th, 2006, 5:32pm

Your loop gain is too low. Please check your DC operating point and make sure your PMOS is in saturation.

The loop gain equation is gm1*R1*gm2*Z*R1/(R1+R2)