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Design >> Analog Design >> Noise Budget in Pipelined ADC
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Message started by reactgary on May 21^st, 2006, 8:35pm

Title: Noise Budget in Pipelined ADC
Post by reactgary on May 21^st, 2006, 8:35pm

Hi all,

What total input refered noise level should we keep in a ADC design, should it be
less than 1/2 of the Qutanizational noise of the adc, or it should be ok if it is
less than Qnoise of the ADC?

Thanks
Gary

Title: Re: Noise Budget in Pipelined ADC
Post by ywguo on May 22^nd, 2006, 9:36pm

Gary,

The budget depends on how much SNR or SNDR you want. :)

Best regards,
Yawei

Title: Re: Noise Budget in Pipelined ADC
Post by vivkr on May 22^nd, 2006, 11:57pm

Hi Gary,

Another important point to reckon with is the power you are willing to burn. If you want higher SNR, then you will inevitably need much more power. You have to decide the acceptable power consumption along with acceptable SNR levels.

Regards
Vivek

Title: Re: Noise Budget in Pipelined ADC
Post by reactgary on May 23^rd, 2006, 8:23am

Thanks All,

I think I know the key concept about the tradeoff between SNR / Power.
I want to know more about the inherent noise budget in a pipelined ADC.
For example, if I am going to make a 10bit ADC, with 1.5bit / stage,
The Qnoise of the second stage would be (VFS/512)^2/12 <<<<< let it be Qa
So, what is a reasonable choice of the noise budget of the first stage
Someone told me that we should keep it half of Qa.
Is it reasonable? Thanks for all the opinions of you guys!

Gary

Title: Re: Noise Budget in Pipelined ADC
Post by ywguo on May 23^rd, 2006, 9:24pm

Gary,

The Quantization error is (Vfs/1024)^2/12 for a 10 bit ADC. The key point is to keep the overall thermal noise not more than the quantization error.

Best regards,
Yawei

Title: Re: Noise Budget in Pipelined ADC
Post by xaviar on Jul 12^th, 2006, 4:59am

Gray,
you can check in some PH.D dissertation in UC berkerly,in the most case Qnoise is set to be (1/6)*LSB,it will give SNR 1~2dB buget. If you locate Qnoise nearly to (1/2)*LSB,it will make your SNR lower.

Title: Re: Noise Budget in Pipelined ADC
Post by TT on Jul 12^th, 2006, 7:18pm

Gary.

if you do 1.5bit/stage then the noise of the second and third stage may not be neglectible, while having more bits
at the input will reduce the noise requirement of the subsequent stage, though increasing a bit the complexity of
the first stage. Also do not forget to add contribution of the voltage reference which are in practice REALLY not neglectible
and usually requires external caps or high current.

TT

Title: Re: Noise Budget in Pipelined ADC
Post by Sid on Jul 15^th, 2006, 6:08pm

Hi,

It is not power efficient to be limited by Quantization Noise, especially at HIGH resolution/SNR. For example, you will design a 14-bit converter even if you want ENOB = 12 (i.e. SNR = 72 dB). This is because you can reduce the quantization noise to the 14-bit level and allow more thermal noise (hence the caps can be smaller thereby saving power). Of course, if you do this, you will need a higher gain*bandwidth 1st stage OTA to settle to 14-bit level and have 14-bit gain-error. So, the design choice for "how many bits?" is basically made based on whether you save more power by having smaller caps or less "accurate" OTAs?

For the 10-bit case, I guess having quantization noise about equal to thermal noise is probably the way to go.

-Sid

Title: Re: Noise Budget in Pipelined ADC
Post by loose-electron on Aug 3^rd, 2006, 3:16pm

A little thinking here. this is about SNR at each stage, as it relates to the residue of each stage in the pipeline.

More specific, it is the IRN (input referred noise) at each stage.

That said, you might want to build a math model of this. (or even just an Excel spreadsheet with some equations in it.) Keep track of the signal IRN, the residue, and look at the compounding noise vs. gain through each conversion stage.

If you put in the gains, noise, of each stage and the resulting SNR's at each output, you can define an aceptable SNR, and gain a better understanding of the noise down the chain.