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Design >> Mixed-Signal Design >> Using separate core and I/O power connections
https://designers-guide.org/forum/YaBB.pl?num=1148832065

Message started by Marc Murphy on May 28^th, 2006, 9:01am

Title: Using separate core and I/O power connections
Post by Marc Murphy on May 28^th, 2006, 9:01am

Here's where I ask my possibly stupid questions and get great answers! Hey, at least I'm learning! :)

When you have a chip with separate core and I/O Vdd/gnd pairs are these connected externally to one single voltage source? E.g. you use one set of terminals on the power supply to connect to all 4 pins?

Thanks,
Marc

Title: Re: Using separate core and I/O power connections
Post by mikki33 on May 28^th, 2006, 9:45am

I'm not sure I exactly understood the question.
In most chips nowdays, core and IO power have different voltage anyway (3.3V and 1.2V).

If you are asking about separation of IO and core with the same voltage, especially digital IO and analog core,
you need the best separation. So, ideally, you put 2 regulators on the board and the board laid-out with 2 different ground planes and 2 different power planes. If it is impossible to put 2 regulators, use one, but keep different ground and power planes all the way to the regulator.

Was it the answer to you question?

Title: Re: Using separate core and I/O power connections
Post by Marc Murphy on May 28^th, 2006, 11:49am

Not quite yet I think...my apologies for not writing up the problem clearly enough!

In this case both the I/O and core voltages are the same.

My question is really about how to supply power to this chip.

If I have a chip that uses separate core and I/O connections which are nominally at 1 V, and this chip has 4 pins - 1Vcore, gndcore, 1VIO, gndIO, how do I power up this chip?

Do I short the 1V pairs and short the gnd pairs, using a single 1 V supply? Or do I need 2 supplies each set at 1 V, connected to the core and IO pin pairs? If the latter is the case, I'm not clear on how ground is defined for the circuit. Don't the grounds need to be connected somewhere to have a common reference?

Thanks,
Marc

Title: Re: Using separate core and I/O power connections
Post by ACWWong on May 28^th, 2006, 1:46pm

Marc Murphy wrote on May 28^th, 2006, 11:49am:

Do I short the 1V pairs and short the gnd pairs, using a single 1 V supply? Or do I need 2 supplies each set at 1 V, connected to the core and IO pin pairs? If the latter is the case, I'm not clear on how ground is defined for the circuit. Don't the grounds need to be connected somewhere to have a common reference?

Thanks,
Marc

You can do either, but unless there is a very clear reason (different voltage or power supply isolation/crosstalk issues etc.) then both supplys and both grounds can come from one supply.
If you use seperate supplies, still it is often they will share the PCB ground reference.

Usually although a chip may have several grounds supplies, often each domain has a substrtae connections somewhere in the die, which nominally means each ground pins is connected together electrically via the substrate (in some chip power/ESD strategies one does NOT do this). Anyway, even though they have nominally the same potential, the grounds can still be isolated from one another in terms of impedance (by deep trenches, substrate isolation structures, phyiscal die distance).

Title: Re: Using separate core and I/O power connections
Post by Marc Murphy on May 28^th, 2006, 2:25pm

Thanks guys! That has set me straight. :)

Title: Re: Using separate core and I/O power connections
Post by mikki33 on May 29^th, 2006, 1:10am

I would suggest, not to define you ground connections as GLOBALs. You can use different VSS's in the chip. Let's say VSS_CORE and VSS_IO. To separate them in the chip (for LVS) use the bulk separation layer (I think it is called PSUB or like that in TSMC).

Use also 2 different ground and power planes on the board and connect them together only very close to the voltage regulator.

Separation of the supplies also required special care about ESD protection. You need to think what will happen when you are zapping VDD_CORE <-> VSS_IO, VDD_CORE <-> VDD_IO... Do you have the discharge path or the current will find its own way and will burn out the chip.

Michael