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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Rough size estimation of decimator for delta-sigma https://designers-guide.org/forum/YaBB.pl?num=1149155165 Message started by shpongle on Jun 1st, 2006, 2:46am |
Title: Rough size estimation of decimator for delta-sigma Post by shpongle on Jun 1st, 2006, 2:46am Hi, I need to have a rough estimation of the equivalent number of gates required to design a decimator for a delta-sigma converter. Is there any "good practice rule" which gives an estimation of the number of equivalent gates based on the filter order, word length, ... ? or do I have to size the decimator i.e. partition into 2-3 decimation stages, specify each filter, write some verilog/vhdl and ask an EDA synthesizer tool for the estimation of gates using NAND logic ? Any hints, information is welcome and greatly appreciated |
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