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Design >> Analog Design >> Signal detector design
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Message started by always@smart on Jun 1^st, 2006, 5:55am

Title: Signal detector design
Post by always@smart on Jun 1^st, 2006, 5:55am

Dear all,

I need to design a Signal detector which detecting the signal swing(Common mode Input =1.2V, Minimum Swing=100mV, Speed=1.25Gbps, Total current consumption <=20uA), can someone suggest me a good idea?

Thanks in advance

Rgd,
Smart

Title: Re: Signal detector design
Post by mikki33 on Jun 1^st, 2006, 7:56am

You may use multipliers: 1. making v^2 of input signal and taking it to the LPF (envelope detector).
2. making Vref^2. 3. Compare these 2 outputs in comparator, output is signal detect.

Title: Re: Signal detector design
Post by ACWWong on Jun 1^st, 2006, 8:25am

the common-emitter (common-source) of a long tail pair will give you a rectified version of the input which you can compare in a comparator... ie typically how RSSI stages are done.

Title: Re: Signal detector design
Post by always@smart on Jun 1^st, 2006, 8:31am

mikki33 wrote on Jun 1^st, 2006, 7:56am:

You may use multipliers: 1. making v^2 of input signal and taking it to the LPF (envelope detector).
2. making Vref^2. 3. Compare these 2 outputs in comparator, output is signal detect.

Dear Mikki33,

Thanks for ur reply.

What kind of multiplier do you mean? Please refer me some material.

How much the total current consumption u will estimate for the design you mentioned?

v^2 of input signal and Vref^2

Do you mean squaring the voltage?

Regards
Smart

Title: Re: Signal detector design
Post by always@smart on Jun 1^st, 2006, 8:45am

ACWWong wrote on Jun 1^st, 2006, 8:25am:

the common-emitter (common-source) of a long tail pair will give you a rectified version of the input which you can compare in a comparator... ie typically how RSSI stages are done.

Thanks ACWWong,

can you please describe in more detail:

the common-emitter (common-source) of a long tail pair will give you a rectified version of the input

Is it a peak detector, which a long tail paraller with a cap to abstract the peak here? But how can it mentain the same peak with PVT change of the input NMOS pair?

Regards,
Smart

Title: Re: Signal detector design
Post by mikki33 on Jun 1^st, 2006, 10:12am

Yes, indeed, it is squaring the voltage. You are taking a multiplier and feed into its 2 inputs the same input signal and get square of it at the output.

For multiplier you may use kind of Gilbert cell.
I am not at the office rigt now, when I'll be back I'll check the exact references. Meanwhile you may search in the internet "squaring circuit" and "analog multiplier".

About current consumption I have no idea. It depends on the process and voltage. If you have 0.13 with low Vt and 1.2 V supply it will be much better then 0.35 with 3.3 V supply.
On 0.13 such a circuits may work up to 10 G.

Have a nice weekend,
Michael

Title: Re: Signal detector design
Post by ACWWong on Jun 1^st, 2006, 3:35pm

always@smart wrote on Jun 1^st, 2006, 8:45am:

Basically I mean you use the full wave recified signal at the common-source node of NMOS pair (at the current source drain), feed that into a comparator to get an input signal dependant current output, which is then summed in cap, and compared with a reference voltage. But as you said to guarantee the 100mV input signal trip point accurately is tricky over PVT (The last time I designed something like this, i used some TRIM bits and a calibration routine...)

Anyway another way as mikki has suggested in the multplier apprach, but I would also try the unbalanced source coupled pair rectifying transconductor as used by the references below:

http://eceserv0.ece.wisc.edu/~sharmav/bluetooth/PowerAmp.pdf
p19 has the unbalanced source soupled pair approach
p18 has the multiplier appraoch.

A CMOS logarithmic IF amplifier with unbalanced source-coupled pairs
Kimura, K.; Solid-State Circuits, IEEE Journal of , Volume: 28 Issue: 1 , Jan. 1993
A 450MHz CMOS RF Power Detector: Stacy Ho. RFIC symposium 2001.

Finally may I add accurate signal level detection @1.25Gbps @ <20uA sounds VERY tough... even in super fast 0.13um CMOS.....

Title: Re: Signal detector design
Post by always@smart on Jun 1^st, 2006, 10:30pm

Thanks ACWWong and mikki33,

The design you both suggest is indeed a good idea.

I more worry on the total current consumption, both Gilbert cell and unbalanced source soupled pair approach is hard to be achieved within 20uA (even excluding comparator) @ 1.25Gbps (vdd=3.0~3.6, 0.18um process)

I may focus on the simplest rectifier (with a NMOS pair input, tail with large RC) and output feed to comparator with hysterisis.

Does anyone has idea how to compensate the PVT variation for the rectifier i have mention above without external trimming component?

regards,
smart

Title: Re: Signal detector design
Post by mikki33 on Jun 2^nd, 2006, 1:40am

always@smart wrote on Jun 1^st, 2006, 10:30pm:

Does anyone has idea how to compensate the PVT variation for the rectifier i have mention above without external trimming component?

Band gap and PTAT... But this is not a good idea...

Gilbert cell itself will also not suit. 3 transistors in series will not work good. What I thought was a cell like Gilbert, which for sure work good with 1.8 supply, somthing like the cell below. You can easily develop analitical expressions and choose sizing.

Michael