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Modeling >> Behavioral Models >> veriloga model for esd pads
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Message started by mengm0411 on Jun 7^th, 2006, 5:02am

Title: veriloga model for esd pads
Post by mengm0411 on Jun 7^th, 2006, 5:02am

I'm trying to establish veriloga model for ESD pads based on their TLP data, where Current is a multi-valued function of voltage for some current range, i.e, there is negative differential resistance (voltage decreases when current increases) or snapback region, as shown in the attached figure. This nature is easily leading to convergence problem: I got "timestep too small" and the simulation terminated. Can anyone give me a hint in how to effectively model this ESD behaviour? Thanks.

Title: Re: veriloga model for esd pads
Post by Jess Chen on Jun 7^th, 2006, 8:26am

Yikes! Your IV curve looks like a modeling nightmare. However, have you tried turning the curve on its side? i.e. have you tried modeling it as a current controlled voltage, v(i), instead of a voltage controlled current source, i(v)?

-Jess

Title: Re: veriloga model for esd pads
Post by Geoffrey_Coram on Jun 7^th, 2006, 1:01pm

You might want to have a look at:

"Compact Modeling of On-Chip ESD Protection Devices Using Verilog-A"
[ J. Li, S. Joshi, R. Barnes, and E. Rosenbaum ]
http://ieeexplore.ieee.org/iel5/43/34175/01629139.pdf?isnumber=34175&arnumber=1629139

I have a philosophical objection to the use of the analysis() function to introduce a different set of equations for ac analysis, but it's at least something published to start from.

I'll also note that the TLP data is *not* a dc i/v curve. TLP applies pulses of increasing voltage, then measures the I and V at some fixed time after the pulse is applied. You'll want to understand that and make sure your circuit simulation is set up to mimic it.

Title: Re: veriloga model for esd pads
Post by NKS on May 25^th, 2007, 4:52am

Hmmm... :-? your comment below about "a philosophical objection to the use of the analysis() function ..." seems to suggest that the authors have made public their Verilog-A source code, somewhere. Am I correct about this? If so, could you tell me where I can get a copy? Thanks in advance.

Geoffrey_Coram wrote on Jun 7^th, 2006, 1:01pm:

Title: Re: veriloga model for esd pads
Post by Geoffrey_Coram on May 25^th, 2007, 8:38am

As I recall, the outline of the V-A model is available in the paper I cited, or another by one of the authors. The full model, though, is not available (except maybe to SRC members?).

Title: Re: veriloga model for esd pads
Post by NKS on May 28^th, 2007, 4:40pm

Geoffrey,

Thank you for the info.

8-)

Title: Re: veriloga model for esd pads
Post by NKS on Jun 12^th, 2007, 11:03pm

Does anyone know how stable the model described in the paper is? I've been coding a Verilog-a code based on the outline described in the paper for some time, now. So far, I have been able to make it exhibit the snapback phenomenon for ggNMOS (Vgs=0) case as shown in the figure below. However, I was only able to get to this point per lots of parameter tweaking. Without tweaking, a simulation run generally ends up in convergence error as shown in the same figure for Vgs=0.5V case.

Upon reading the paper, I got the impression that the equations shown in the paper do not induce severe convergence problems. What common mistakes would I be making?

Specifically I have following questions:

1. What are the values for the parameters that would result in reasonably similar results as the plots shown in the paper; I've tried to contact one of the authors about
this matter but did not receive any response. For example, p1, p2, p3, A, B, I_oc, Iob, R_sub, R_on, C_GD, C_Db, C_GS, C_Sb, C_Gb, Tox, Mu_eff.
2. Do I need to check some condition(ex. voltages across some nodes) before executing the equations in Table II?
3. How good (low convergence error occurence and reasonable precision) is this approach of behavior modeling ESD devices? Is the difficulty with simulation convergence
inevitable with this kind of approach? Or am I missing some subtilties with my coding.

Thanks in advance.

NKS :(