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Design >> RF Design >> IIP3 Simulation
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Message started by uncle_ezra on Jun 7^th, 2006, 6:32am

Title: IIP3 Simulation
Post by uncle_ezra on Jun 7^th, 2006, 6:32am

To test RF Front-end IIP3 I input two tones and run transient analysis. How far apart should the two tones be 1MHz, 5MHz? What is the rule?

Thanks

Title: Re: IIP3 Simulation
Post by ACWWong on Jun 7^th, 2006, 7:18am

...depends on the bandwidth of the system you are looking at. Generally one is interested in the in-band effects of two tones, so you should ensure they are close enough together to enusre inband response.. but usually far enough away to improve simulation time. e.g a if the bandwidth is 10MHz, spacing the tones at 1MHz or 5MHz should give the same result (any difference may be due to small effects like passband reponse ripple or LO phase noise etc.) but 5MHz would be qicker to simulate!

Title: Re: IIP3 Simulation
Post by uncle_ezra on Jun 13^th, 2006, 9:02pm

So I ran P1dB for RF Front-end and found that P1dB from Mixer input to output is the bottleneck. Where would the bottleneck likely be in the mixer? Input Gm or output? How can I improve Mixer linearity other than increasing the input Gm overdrive? I am using resistor as my loading.

Thanks

Title: Re: IIP3 Simulation
Post by ACWWong on Jun 14^th, 2006, 3:06am

The bottleneck could be either the input or the output. Depending on your system lineup will depend on whether you care about output compression/clipping. You may find the following stage from the mixer may have an input compression far lower (6dB or more) than your mixer's output compression so you shouldn't care about output clipping in that case.

Anyway to see whether output clipping is the problem, often I artificaly increase the power supply to allow the output enough headroom to swing freely, and see whether the compression eases (of course in conjunction with hand calculations as to what the linearity should be based upon device overdrive etc.). This simulation approach will be especially effective given you are resistively loaded (up to vdd i guess). If using gilbert style mixer, one should take care that DC bias of the commutating state is optimised.

Ways to increase input compression without decreasing gain (or increasing noise) is problematic unless you have more current. Typical methods as well as increaing over drive are degeneration (either resistive or inductive) or doublets/triplets (offset pairs the same as multi-tanh in BJT technology). I have used both these methods and found both have advantages and disadvantages, but both work well. There are other ways to do this, most RF books (like Tom Lee's "The Design ofCMOS Radio Frequency Integrated Circuits" deisgn book).

Anyway hope this helps.

Title: Re: IIP3 Simulation
Post by uncle_ezra on Jun 14^th, 2006, 6:55pm

I have found that increasing the current going into the switches improves P1dB. I am using a gilbert cell mixer with PMOS current bleeding. So basically I decreased the PMOS bleeding current to increase the current going into the switches. This comes at the expense of noise degradation.

You mention the DC bias of the commutating state should be optimised. You mean the gate bias should be below the output bias point? Can you explain more about this?

Thanks

Title: Re: IIP3 Simulation
Post by ACWWong on Jun 26^th, 2006, 10:37am

The optimum DC operating point for the LO quad gates will depend on the drain (output volts drop across the load) and the operating point of the gm transistors (btm tier). For any given situation I usually sweep the DC operating point to find the optimum situation.... so i don't mean that the gate bias should be below the output bias point, as for example this can cause the input gm transistors to come out of saturation.
Anyway when you say you decreased the current in the PMOS bleed to improve the P1dB, the gain decreased right ?
cheers
aw

Title: Re: IIP3 Simulation
Post by uncle_ezra on Jul 4^th, 2006, 10:25pm

Basically my bottleneck was at the switching stage and output stage. The IIP3 of the switching stage depends on the current through, so I increased the current through it at the cost of noise. Also the output resistor was reduced since the voltage swing at the output modulates the switching transistor. So overall you are right, it comes at the cost of gain.

Thanks !!