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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Basic Verilog-A question https://designers-guide.org/forum/YaBB.pl?num=1150031452 Message started by carbonnanotube on Jun 11th, 2006, 6:10am |
Title: Basic Verilog-A question Post by carbonnanotube on Jun 11th, 2006, 6:10am Hi everybody, I'm rather new to the topic of Verilog-A modelling; thus, I'm playing ariound with some simple models in order to get a feeling for the concepts. Doing so, I encountered a (in my opinion) strange "effect": I modelled a simple circuit (R parallel C) and simulated with Cadence Spectre: module simpleRC(A, B); electrical A, B; branch (A, B) Cap; branch (A, B) Res; parameter real R = 1e3; parameter real C = 1e-6; analog begin I(Cap) <+ ddt(V(Cap))*C; V(Res) <+ I(Res)*R; end endmodule which works fine. Then I change the model to the following: module simpleRC(A, B); electrical A, B; branch (A, B) RC; parameter real R = 1e3; parameter real C = 1e-6; analog begin V(RC) <+ I(RC)*R; I(RC) <+ ddt(V(RC))*C; end endmodule which still works (!!). That is confusing for me as I expected that the RC-Branch switches to be a flow branch representing a C only (without the parallel R). Could anybody kindly clear this up? Regards, Oliver |
Title: Re: Basic Verilog-A question Post by Ken Kundert on Jun 11th, 2006, 8:27am It seems wrong to me too. I suggest you talk to Cadence about it. Please post their response. -Ken |
Title: Re: Basic Verilog-A question Post by Geoffrey_Coram on Jun 12th, 2006, 4:01am Indeed, the branch value retention rules (see Section 5.3.1.3 in the Verilog-AMS LRM version 2.2) indicate that the module should act as just a capacitor; the potential contribution should be discarded. |
Title: Re: Basic Verilog-A question Post by carbonnanotube on Jun 12th, 2006, 6:05am Thanks for the information. Quote:
Unfortunately, we don't have Cadence support (we are a university using Europractice). Thus, I see no way to discuss that problem with Cadence directly. -Oliver |
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