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Design >> RF Design >> Surge/ESD Protection for RF circuit
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Message started by hrkhari on Jun 13^th, 2006, 12:20am

Title: Surge/ESD Protection for RF circuit
Post by hrkhari on Jun 13^th, 2006, 12:20am

Hi Guys:

When I design the RF circuit, I would include a reversed biased diode model at the I/O port for surge protection. This is illustrated in Figure.1 where a complete I/O model used is presented.

I had received a feedback for an ESD designer to increase the number of series connected diodes to decrease the effective capacitance at the I/O for RF signals, is it advisable to do so?.

I had also received an advise from the foundry to include a p-n junction reversed biased diode at each of the transistor gates in the circuit ad in Figure. 2. Is it advisable to do so?. Would it effect the performance of the designed circuit?.

I highly appreciate your kind assistance. Thanks in advance

Rgds
Harikrishnan

Title: Re: Surge/ESD Protection for RF circuit
Post by milkdragon on Jun 13^th, 2006, 10:34am

Yes, it does affect the performance of the circuit. Stacking up more diode is to prevent any forward biasing it with a large signal, of course, at the expense of the ESD performance. Typically trade off is made here on the RF performance and the ESD performance. The foundry was rite by putting one more diode near the gate for CDM clamp for further protection. However, typically it is used in conjunction with some resistance between I/O pad and the input device. If CDM is your concern, then you should add this diode. However, as far as i know, most people ignore it for RF operation.