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Design >> Analog Design >> CMOS Bandgap: Why high area BJTs?
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Message started by ipsc on Jun 25^th, 2006, 11:51am

Title: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jun 25^th, 2006, 11:51am

Hi,

What decides the area of BJTs we use in bandgap references?

Why do we generally use large area BJTs in CMOS bandgap references?

Can somebody please answer these?

Thanks.

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by Croaker on Jun 25^th, 2006, 12:13pm

This is just a guess:

Vbe=Vt*ln( I/(Is*A) ), so the larger the device is, the less the area variations will affect Vbe; you get a better-defined Vbe for a given I.

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ace on Jun 27^th, 2006, 2:04am

i think matching is fairly important, as one usually uses area ratioing to produce a deltaVbe term (the PTAT part) and then another bjt for the CTAT part. using large area devices allows for perhaps better matching of devices (especially of Is which is function of temp)
additionally in CMOS it usually pretty inevitable the bjt parts are large beacuse they are parasictic devices so aren't optimised for small size/contact areas.

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jun 27^th, 2006, 11:24am

Hi,

Above reasons seem reasonable to me.

But now, I was told that it is mainly to reduce the base resistance, which is large for vertical PNPs of CMOS technology. If so, it's not clear to me 'how high base resistance will affect the bandgap performance?'.

Any idea?

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ACWWong on Jun 29^th, 2006, 3:50am

if noise is important, then having low rb will help... but in most bandgaps, it is not usually the dominating noise term...

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by mikki33 on Jun 30^th, 2006, 1:02am

I think there is a number of considerations here.

First and most practicle is what transistor (model and layout) you are getting from the foundary with the design kit.
I still remember times when the only one was 10X10. Now you may have others like 5X5 and 2.5X2.5. If your drsign was originated some time back and was silicon proved in previous processes (like 1 μm, 0.5, 0.35, 0.25 etc), why to change?

2. The β of parasitic bipolar transistor is very low and varies with I_CE. The β graph has some bell like curve, where the maximum is the preffered operating point. For small transistors, current which gaves max β may be low (let's say 1-3 μA), so you band-gap will be very mismatch sensitive. If you operates your band gap with higher currents, it will not be the band gap which your are expected to see, it will have too steep temperature curve.

3. R_b is also playing the role here. If you have small transistors, ratio of parasitic R_b and your designed resistor are growing and reducing you band gap abilities (more steap curve, more PVT sensitivity, more wafers/lots statistical spread). It is interesting to note that some time back for one of my previous emloyers I designed the small circuit to compensate R_b influence and R_b variation...

Hope, this explains something,
Michael

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by jcpu2006 on Jul 2^nd, 2006, 10:57pm

mikki33 wrote:
Rb is also playing the role here. If you have small transistors, ratio of parasitic Rb and your designed resistor are growing and reducing you band gap abilities (more steap curve, more PVT sensitivity, more wafers/lots statistical spread).

Dear Sir:
I have been seriously looking into BGR wafers/lots statistical spread.
Large Rb, to me seems to be systematic error intuitively.
Please teach more detail how does it cause statistical spread.

Thanks in advance.

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jul 3^rd, 2006, 1:27pm

Thanks Michael, for your very detailed answer. But few things are not clear to me. Can you please explain?

1. Why do we need to bias a BJT at high β? Since in a CMOS bandgap emitter current and not the collcetor current
is used to obtain ΔVBE, I think, β value should not matter.
However I think, low β coupled with high RB might cause some problem as vb of two BJTs
will not be at zero and MAY not be EQUAL. Am I right?

2. I have checked RB, RE, and RC values for 2X2um, 5x5um and 10X10um BJTs of 0.15um TSMC technology.
To my suprise I found that RB and RC values are almost same for all, though RE decreases as the size increases.
I think, thus one is not getting any benifit by going to high area from Rb perspective alone. :exclamation :-/

3. I am eager to know the method to compensate Rb effect. Can you please
post it?

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ywguo on Jul 3^rd, 2006, 7:27pm

hi, ipsc,

As Michael said,
Quote:

The β graph has some bell like curve, where the maximum is the preffered operating point.

At the top of the bell like curve, the emitter current has good exponential relationship with Vbe. That's where the operation principle of BGR orginated.

I am curious that RB and RC values are almost same for all, though RE decreases as the size increases. I will check my design, which is designed in SMIC 0.13um process. It has good temprature curve, but it spreads very large at TT, SS, and FF corners.

Best regards,
Yawei

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by mikki33 on Jul 4^th, 2006, 8:48am

jcpu2006 wrote on Jul 2^nd, 2006, 10:57pm:

I have been seriously looking into BGR wafers/lots statistical spread.
Large Rb, to me seems to be systematic error intuitively.
Please teach more detail how does it cause statistical spread.

Larger R_b means larger variation of the difference of R_b and R_b/10 (if you are using 1:10 transistors ratio). That means ΔV_be varies more. And your band gap voltage depends more on doping density which is the changing process parameter. (different wafers and different lots)

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by mikki33 on Jul 4^th, 2006, 9:06am

ipsc wrote on Jul 3^rd, 2006, 1:27pm:

3. I am eager to know the method to compensate Rb effect. Can you please
post it?

It is to reduce the variation of ΔV_be with process and temperature. The bases of all 10 transistors were shorted and I used net of small diffusion or poly resistors (beleive me, I don't remember, it was so many yeras ago...) to connect them to the ground. I wrote some matlab to make optimizations and run perl to generate sim netlist run spice and read the results back to matlab...
I even don't remember what the silicon results were, I, probably, moved to another project, or left the company, or/and no one bothered to check it.

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by mikki33 on Jul 4^th, 2006, 9:14am

ywguo wrote on Jul 3^rd, 2006, 7:27pm:

It has good temprature curve, but it spreads very large at TT, SS, and FF corners.

It may be the currents variations or your band gap has poor PSRR.
Also it may be worth to check your BJT work point from β point of view...
Does your bipolar transistor has typical/fast/slow model? If it is not, the situation on the silicon will be worse.
In this case you have to "create your own" fast and slow models (all parasitic resistors and β)

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jul 4^th, 2006, 11:08am

ywguo wrote on Jul 3^rd, 2006, 7:27pm:

hi, ipsc,

As Michael said,
Quote:

The β graph has some bell like curve, where the maximum is the preffered operating point.

At the top of the bell like curve, the emitter current has good exponential relationship with Vbe. That's where the operation principle of BGR orginated.

Thanks a lot Yawei. I am not aware of this. I used to bias BJTs to some arbitrary current depending on my power budget. From now on, I will follow this. But I have one doubt. Since I can't bias both BJTs at maximum β, which one, larger or smaller, should I bias at max β?

Thanks

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by RobG on Jul 5^th, 2006, 12:35pm

You don't say what large is.... it seemed 20x20 um^2 used to be the standard. This is way bigger than necessary for matching and just about anything else. The only reason you needed to use that big of a device was because it was the only one that had a model... which is often the case unfortunately.

Smaller dimensions work better all around... they have lower Rb for a given area (i.e. you obtain better performance by putting 10 4x4 devices in parallel instead of one 20x20).

rg

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jul 6^th, 2006, 11:38am

Thanks Rob for your good questions. Let me make my question more clear.

I have seen most fabs mainly providing 5umX5um or 10umX10um devices. (of course now, recently I have seen 2umX2um as well along with 5umX5um for a 0.15um technology. However I was asked to use 5umX5um, as it is the one generally used by my company).

I felt, there must be some reason from BJT or Bandgap performance perspective as well to provide such a high area BJT models. I feel, even 2umX2um for a 0.15um technology is a way bigger than necessary for matching alone.

Your last point brought me an important question. Suppose I have 2umx2um and 5umx5um BJTs. Can I just go and use four 2umX2um instead of one 5umX5um device OR can I just use one 2umx2um for one 5umX5um? If not, what are the parameters in the models that I have to look out for in choosing one of these options?

Regards

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by RobG on Jul 9^th, 2006, 10:43pm

I would guess that a 5x5 device will have an mismatch standard deviatoin on the order of 50uV. That is a very rough number that ignores contact resistance, etc.... I hate to even throw that number out... but the reason I mention it is because it may be significant depending on how you manage the other offsets, most importantly, the opamp offset. Keep in mind that your overall size may be determined by diffusion spacings and not emitter area.

Bipolars don't scale perfectly. You can't expect a 4x4 to behave like four 2x2s even though they have the same area. Smaller area emitters generally result in lower Rb, which means you can run them at a higher current density, which means you'll have a bandgap with less noise. This effect may be pretty small, though.

Bandgap references need a very accurate model. The best bet is to use a device that has some history even if it costs you some area. The reasons for this is the devices are notoriously hard to model. If the device does have a good history, consider running it at the same current density. A lot of bandgap errors occur because the device is run at too high a density so that base resistances and other non-ideal (read poorly modeled) effects contribute overly to the response.

If you don't have a history, or feel you can endure the wrath of your boss for not using a device with history, the best bet is to look at the performance verus current density rather the model parameters which often don't mean much (plus I can't rattle off the important non-ideal ones). To do this, set up an experiment with your various bipolars, each with your desired ratio (e.g. 8:1). As you know, the difference in emitter voltage should be U_T*ln(8) no matter what the current is. Well, sweep the current and watch how that voltage behaves as current increases. You can judge how much current you can run those devices and still be pretty ideal. I generally run them at the point where the votlage changes a few hundred uV above the ideal value.

PS, I made an error in my previous post when I said 10 4x4 devices instead of a 20x20. It should have been 25 4x4 devices since that ill give the same area.

rg

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ipsc on Jul 16^th, 2006, 11:49am

Hi Rob,

Thanks a lot Rob for your detailed reply. It taught me a lot of new things. Can you please suggest any good book for bandgap references?

Regards

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ywguo on Jul 20^th, 2006, 2:53am

ipsc,

There are some good tutorials on www.circuitsage.com. :)

Yawei

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by RobG on Jul 24^th, 2006, 11:18am

I'm glad it was helpful. I don't know of any good references. Rincon-Mora has a book on the subject, but he seemed (to me anyway) to get hung up on circuit cleverness instead of the basics. Lack of cleverness in the circuit isn't the problem with bandgaps... the problems usually come from non-ideal effects that were not modeled correctly (or that are impossible to model). It is really hard to capture all the things that need to go into a robust design... mostly, it is just a lot of experience and attention to details. My advice is, if it doesn't work perfectly in simulation, go find out why. Take the time to understand the important parameters in the model (mostly IS, EG, NF,...) and try to build circuits that aren't sensitive to the non-ideal parameters (Rb, Re, IKF, etc...).

It doesn't capture everything, but Barrie Gilbert wrote a decent chapter in Huijsing's book:
B. Gilbert, “Monolithic voltage and current references: Theme and variations,” Analog Circuit Design, J. H. Huijsing, R. J. van de Plassche, and W. M. C. Sansen, Ed. Dordrecht, The Netherlands: Kluwer, 1996, pp. 269-352.

More than that, and I'd have send you a bill ;-)

rg

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by loose-electron on Aug 1^st, 2006, 6:19pm

Let me note a key thing here: CMOS bandgaps.

That means that you are probably using the collector tied to substrate PNP that is available on P Substrate, single N-well CMOS.

That is a lateral PNP which in addition to having terrible Ft and terrible Beta, it is very resistive. If you get a model that accuratly reflects the resistances inherent to the junctions, you see that you need to keep the currents low, or the junction areas high for the body resistance to not play into the Vbe differences between the large and small junction areas.

A good example of this is the thermal monitor that gets used in all Intel processors. It is monitoring the Vbe of a diode junction on the microprocessor. Due to all the resistance, the external thermal control chip that uses this diode keeps the currents between 10uA and 100uA, otherwise the resistance gets into the equation a bit too much. (starts looking like V=IR instead of V = Vbe)

Big thing in CMOS bandgaps tends to be mismatch of the differential pair in the bandgap amplifier. That tends to dominate the erros of the device. COnsider chopper stabilization or an offset alignment to work around that.

my 2 cents worth...
:D

Title: Re: CMOS Bandgap: Why high area BJTs?
Post by ywguo on Aug 1^st, 2006, 6:35pm

Hi, Michael,

Quote:

Does your bipolar transistor has typical/fast/slow model? If it is not, the situation on the silicon will be worse.
In this case you have to "create your own" fast and slow models (all parasitic resistors and β)

Yes, it has typical/fast/slow model for bipolar transistor. That is a 0.13 um CMOS process. I think that is the reason why the circuit have 3 curves. :)

BG
Yawei